A self-aligned elevated source/drain MOSFET
An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new...
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| Veröffentlicht in: | IEEE electron device letters 1990-09, Vol.11 (9), p.365-367 |
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| container_end_page | 367 |
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| container_issue | 9 |
| container_start_page | 365 |
| container_title | IEEE electron device letters |
| container_volume | 11 |
| creator | Pfiester, J.R. Sivan, R.D. Liaw, H.M. Seelbach, C.A. Gunderson, C.D. |
| description | An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.< > |
| doi_str_mv | 10.1109/55.62957 |
| format | Article |
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Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.< ></description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/55.62957</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; CMOS process ; Electronics ; Etching ; Exact sciences and technology ; Fabrication ; FETs ; MOS devices ; MOSFET circuits ; Semiconductor electronics. Microelectronics. Optoelectronics. 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Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.< ></description><subject>Applied sciences</subject><subject>CMOS process</subject><subject>Electronics</subject><subject>Etching</subject><subject>Exact sciences and technology</subject><subject>Fabrication</subject><subject>FETs</subject><subject>MOS devices</subject><subject>MOSFET circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Silicon</subject><subject>Substrates</subject><subject>Surfaces</subject><subject>Transistors</subject><subject>Voltage</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1990</creationdate><recordtype>article</recordtype><recordid>eNqF0E1LAzEQBuAgCtYqePXWiyLItskmk2yOUvyCSg_qOcxmJ7Ky3a1JK_jvXd2iR08zzDy8h5exU8GnQnA7A5jq3ILZYyMBUGQctNxnI26UyKTg-pAdpfTGuVDKqBG7up4kakKGTf3aUjWhhj5w0y-p20ZPsypi3U4el0-3N8_H7CBgk-hkN8fspb_O77PF8u5hfr3IvJSwyRAsDyWg4ZaUrgovDZVclUHl2nqBRvoSiWTBq6DAFLbiQXmNHhSaUpAcs4shdx279y2ljVvVyVPTYEvdNrm8AG1B2f-hskWRS9XDywH62KUUKbh1rFcYP53g7rs2B-B-auvp-S4Tk8cmRGx9nf68lbkyUvbubHA1Ef2-h4wvwMdyTQ</recordid><startdate>19900901</startdate><enddate>19900901</enddate><creator>Pfiester, J.R.</creator><creator>Sivan, R.D.</creator><creator>Liaw, H.M.</creator><creator>Seelbach, C.A.</creator><creator>Gunderson, C.D.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19900901</creationdate><title>A self-aligned elevated source/drain MOSFET</title><author>Pfiester, J.R. ; Sivan, R.D. ; Liaw, H.M. ; Seelbach, C.A. ; Gunderson, C.D.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c335t-a590fb5a709e46d8c37eb04bf4269c1a73cbaee380df45789d0f4c6ac54a7b1e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1990</creationdate><topic>Applied sciences</topic><topic>CMOS process</topic><topic>Electronics</topic><topic>Etching</topic><topic>Exact sciences and technology</topic><topic>Fabrication</topic><topic>FETs</topic><topic>MOS devices</topic><topic>MOSFET circuits</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><topic>Substrates</topic><topic>Surfaces</topic><topic>Transistors</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Pfiester, J.R.</creatorcontrib><creatorcontrib>Sivan, R.D.</creatorcontrib><creatorcontrib>Liaw, H.M.</creatorcontrib><creatorcontrib>Seelbach, C.A.</creatorcontrib><creatorcontrib>Gunderson, C.D.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pfiester, J.R.</au><au>Sivan, R.D.</au><au>Liaw, H.M.</au><au>Seelbach, C.A.</au><au>Gunderson, C.D.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A self-aligned elevated source/drain MOSFET</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>1990-09-01</date><risdate>1990</risdate><volume>11</volume><issue>9</issue><spage>365</spage><epage>367</epage><pages>365-367</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/55.62957</doi><tpages>3</tpages></addata></record> |
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| identifier | ISSN: 0741-3106 |
| ispartof | IEEE electron device letters, 1990-09, Vol.11 (9), p.365-367 |
| issn | 0741-3106 1558-0563 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_24988234 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences CMOS process Electronics Etching Exact sciences and technology Fabrication FETs MOS devices MOSFET circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Substrates Surfaces Transistors Voltage |
| title | A self-aligned elevated source/drain MOSFET |
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