Turn-on delay analysis of current-injection Josephson logic circuits

A turn-on delay, during which the output voltage of a Josephson logic circuit is very small, is of prime interest for the design of high-speed Josephson digital integrated circuits. We have derived an analytical formula for the turn-on delay of the current-injection logic circuits, which is in good agreement with computer simulations. Analysis of the circuit equations shows that the nonlinear inductance of a current-summing Josephson junction plays an important role for the turn-on delay. Dependences of the turn-on delay on circuit parameters and operating conditions are calculated. For parameter values typical of 5-μm current-injection circuits, the turn-on delay is on the order of 10 ps. The turn-on delay and operating margin are compared in various types of current-injection logic circuits. The higher sensitivity of the threshold gate current to the input current is found to be desirable not only to reduce the turn-on delay but to operate in a wide margin.