0.3- mu m advanced SAINT FET's having asymmetric n super(+)-layers for ultra-high-frequency GaAs MMIC's

Improvements in the microwave and noise performance of BP-SAINT FET's are discussed. Specifically, a self-aligned gate electrode and an asymmetric n super(+)-layer structure are investigated. The self-aligned gate electrode reduces parasitic gate capacitances by 0.13 to 0.23 pF/mm compared with a conventional BP-SAINT FET. The asymmetric n super(+)-layer structure reduces short-channel effects (drain conductance, threshold voltage shift, etc.) and gate-drain capacitance. A 0.3- mu m gate-length FET is realized without an increase of short-channel effects by using an asymmetric n super(+)-layer structure.