Two level cache architectures
The authors discuss the performance measures required in building two-level cache solutions in uniprocessor systems based on more aggressive processors than the Intel486 microprocessor for desktop applications. The performance of serial second level caches is shown to exceed that of parallel caches...
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| creator | Azimi, M. Prasad, B. Bhat, K. |
| description | The authors discuss the performance measures required in building two-level cache solutions in uniprocessor systems based on more aggressive processors than the Intel486 microprocessor for desktop applications. The performance of serial second level caches is shown to exceed that of parallel caches by 10%-20%. The effect of second-level cache parameters such as cache/line/associativity/sector sizes is examined. It is shown that, as long as one of the two caches in the cache hierarchy is operating in the write back mode, the performance will be close to the case of both functioning in the write back mode. The authors quantify the fact that second-level caches reduce memory latency sensitivities. The performance gain of a full speed interface between the two levels of the cache hierarchy versus a half speed interface is shown to be about 10% for desktop applications.< > |
| doi_str_mv | 10.1109/CMPCON.1992.186736 |
| format | Conference Proceeding |
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| identifier | ISBN: 9780818626555 |
| ispartof | COMPCON Spring '92 - 37th IEEE International, 1992, p.344-349 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Delay Engines Frequency Microprocessors Paper technology Performance analysis Performance gain Random access memory Trademarks |
| title | Two level cache architectures |
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