Determination of the energy distribution of interface traps in MIS systems using non-steady-state techniques

Experimental techniques are described for determining the energy distribution of interface traps at the semiconductor-insulator interface of MIS devices. The device used here was an MNOS capacitor in which the semiconductor was n-type. The first technique which is described is that of measuring the thermally stimulated currents. The method consists of biasing the capacitor into the accumulation mode at a low temperature thereby filling the traps at the semiconductor oxide interface. The device is then biased into the deep-depletion mode in which state the traps remain filled because the temperature is too low to allow the electrons to be thermally excited out of the traps. The temperature of the device is then raised at a uniform rate, and the current associated with the release of electrons from the trap is monitored. The shape of the I−T characteristic is a direct image of the interface trap distribution is a broad peak with a maximum at 0·35 eV below the bottom of the conduction band, and of height approximately 6 × 10 13 cm −2eV −1. The experiments were carried out at two heating rates (0·1°K/sec and 0·01°K/sec), and the trap densities so obtained were identical. The second method consists of biasing the device into the accumulation mode at a fixed temperature thereby filling the traps at the silicon-silicon oxide interface. It is then short-circuited and the non-steady state transient current associated with the release of electrons from the interface traps is monitored. The energy distribution of the interface traps in the upper half of the forbidden gap is shown to be readily obtained from the transient currents, and is found to be identical to that obtained using the thermal technique.