NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps

Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for sin...

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Veröffentlicht in:IEEE transaction on neural networks and learning systems 2019-03, Vol.30 (3), p.644-656
Hauptverfasser: Aimar, Alessandro, Mostafa, Hesham, Calabrese, Enrico, Rios-Navarro, Antonio, Tapiador-Morales, Ricardo, Lungu, Iulia-Alexandra, Milde, Moritz B., Corradi, Federico, Linares-Barranco, Alejandro, Liu, Shih-Chii, Delbruck, Tobi
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container_title IEEE transaction on neural networks and learning systems
container_volume 30
creator Aimar, Alessandro
Mostafa, Hesham
Calabrese, Enrico
Rios-Navarro, Antonio
Tapiador-Morales, Ricardo
Lungu, Iulia-Alexandra
Milde, Moritz B.
Corradi, Federico
Linares-Barranco, Alejandro
Liu, Shih-Chii
Delbruck, Tobi
description Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from 1\times 1 to 7\times 7 . NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm 2 . As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations.
doi_str_mv 10.1109/TNNLS.2018.2852335
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subjects Artificial intelligence
Artificial neural networks
Computer architecture
Computer memory
Computer simulation
computer vision
convolutional neural networks (CNNs)
Efficiency
Feature extraction
Feature maps
Field programmable gate arrays
field-programmable gate array (FPGA)
Graphics processing units
Hardware
Information processing
Kernel
Latency
Neural networks
Pipelines
Power efficiency
Sparsity
State of the art
Training
Visual tasks
VLSI
title NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps
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