NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps
Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for sin...
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Veröffentlicht in: | IEEE transaction on neural networks and learning systems 2019-03, Vol.30 (3), p.644-656 |
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creator | Aimar, Alessandro Mostafa, Hesham Calabrese, Enrico Rios-Navarro, Antonio Tapiador-Morales, Ricardo Lungu, Iulia-Alexandra Milde, Moritz B. Corradi, Federico Linares-Barranco, Alejandro Liu, Shih-Chii Delbruck, Tobi |
description | Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from 1\times 1 to 7\times 7 . NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm 2 . As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations. |
doi_str_mv | 10.1109/TNNLS.2018.2852335 |
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Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from <inline-formula> <tex-math notation="LaTeX">1\times 1 </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">7\times 7 </tex-math></inline-formula>. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm 2 . As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations.]]></description><identifier>ISSN: 2162-237X</identifier><identifier>EISSN: 2162-2388</identifier><identifier>DOI: 10.1109/TNNLS.2018.2852335</identifier><identifier>PMID: 30047912</identifier><identifier>CODEN: ITNNAL</identifier><language>eng</language><publisher>United States: IEEE</publisher><subject>Artificial intelligence ; Artificial neural networks ; Computer architecture ; Computer memory ; Computer simulation ; computer vision ; convolutional neural networks (CNNs) ; Efficiency ; Feature extraction ; Feature maps ; Field programmable gate arrays ; field-programmable gate array (FPGA) ; Graphics processing units ; Hardware ; Information processing ; Kernel ; Latency ; Neural networks ; Pipelines ; Power efficiency ; Sparsity ; State of the art ; Training ; Visual tasks ; VLSI</subject><ispartof>IEEE transaction on neural networks and learning systems, 2019-03, Vol.30 (3), p.644-656</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from <inline-formula> <tex-math notation="LaTeX">1\times 1 </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">7\times 7 </tex-math></inline-formula>. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm 2 . As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations.]]></description><subject>Artificial intelligence</subject><subject>Artificial neural networks</subject><subject>Computer architecture</subject><subject>Computer memory</subject><subject>Computer simulation</subject><subject>computer vision</subject><subject>convolutional neural networks (CNNs)</subject><subject>Efficiency</subject><subject>Feature extraction</subject><subject>Feature maps</subject><subject>Field programmable gate arrays</subject><subject>field-programmable gate array (FPGA)</subject><subject>Graphics processing units</subject><subject>Hardware</subject><subject>Information processing</subject><subject>Kernel</subject><subject>Latency</subject><subject>Neural networks</subject><subject>Pipelines</subject><subject>Power efficiency</subject><subject>Sparsity</subject><subject>State of the art</subject><subject>Training</subject><subject>Visual tasks</subject><subject>VLSI</subject><issn>2162-237X</issn><issn>2162-2388</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2019</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkUtLAzEUhYMoVmr_gIIE3LhpzauZibtarBVqBVvB3ZCZuQOj6WRMZnz8e9OHXZjNCeQ7h3tzEDqjZEApUdfL-Xy2GDBC4wGLh4zz4QE6YVSyPuNxfLi_R68d1PP-jYQjyVAKdYw6nBARKcpOkJm3xkxtfYNHeGLgu0wN4LGtPq1pm9JW2uA5tG4jzZd173iUZWDA6cY6fKs95NhWeFFr5wE_Q-3AQ9XotddjW-AJ6KZ1gB917U_RUaGNh95Ou-hlcrccT_uzp_uH8WjWzwQhTV_JvCCCKCFyqaMo16IgXEYxFxmQSBKppUplphRQHYuU5rJI84zlhA9ZIRjwLrra5tbOfrTgm2RV-jC10RXY1icspCjKJWMBvfyHvtnWhbUDRWMRRZxzGSi2pTJnvXdQJLUrV9r9JJQk6zqSTR3Juo5kV0cwXeyi23QF-d7y9_kBON8CJQDsn2PBQiDnvwIhje8</recordid><startdate>20190301</startdate><enddate>20190301</enddate><creator>Aimar, Alessandro</creator><creator>Mostafa, Hesham</creator><creator>Calabrese, Enrico</creator><creator>Rios-Navarro, Antonio</creator><creator>Tapiador-Morales, Ricardo</creator><creator>Lungu, Iulia-Alexandra</creator><creator>Milde, Moritz B.</creator><creator>Corradi, Federico</creator><creator>Linares-Barranco, Alejandro</creator><creator>Liu, Shih-Chii</creator><creator>Delbruck, Tobi</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Mostafa, Hesham ; Calabrese, Enrico ; Rios-Navarro, Antonio ; Tapiador-Morales, Ricardo ; Lungu, Iulia-Alexandra ; Milde, Moritz B. ; Corradi, Federico ; Linares-Barranco, Alejandro ; Liu, Shih-Chii ; Delbruck, Tobi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c400t-96df040944d6a77da4f0367834ce07606a69b6c99e1a84b1d6fbdc2d0352f42e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2019</creationdate><topic>Artificial intelligence</topic><topic>Artificial neural networks</topic><topic>Computer architecture</topic><topic>Computer memory</topic><topic>Computer simulation</topic><topic>computer vision</topic><topic>convolutional neural networks (CNNs)</topic><topic>Efficiency</topic><topic>Feature extraction</topic><topic>Feature maps</topic><topic>Field programmable gate arrays</topic><topic>field-programmable gate array (FPGA)</topic><topic>Graphics processing units</topic><topic>Hardware</topic><topic>Information processing</topic><topic>Kernel</topic><topic>Latency</topic><topic>Neural networks</topic><topic>Pipelines</topic><topic>Power efficiency</topic><topic>Sparsity</topic><topic>State of the art</topic><topic>Training</topic><topic>Visual tasks</topic><topic>VLSI</topic><toplevel>online_resources</toplevel><creatorcontrib>Aimar, Alessandro</creatorcontrib><creatorcontrib>Mostafa, Hesham</creatorcontrib><creatorcontrib>Calabrese, Enrico</creatorcontrib><creatorcontrib>Rios-Navarro, Antonio</creatorcontrib><creatorcontrib>Tapiador-Morales, Ricardo</creatorcontrib><creatorcontrib>Lungu, Iulia-Alexandra</creatorcontrib><creatorcontrib>Milde, Moritz B.</creatorcontrib><creatorcontrib>Corradi, Federico</creatorcontrib><creatorcontrib>Linares-Barranco, Alejandro</creatorcontrib><creatorcontrib>Liu, Shih-Chii</creatorcontrib><creatorcontrib>Delbruck, Tobi</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>PubMed</collection><collection>CrossRef</collection><collection>Aluminium Industry Abstracts</collection><collection>Biotechnology Research Abstracts</collection><collection>Calcium & Calcified Tissue Abstracts</collection><collection>Ceramic Abstracts</collection><collection>Chemoreception Abstracts</collection><collection>Computer and Information Systems Abstracts</collection><collection>Corrosion Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Engineered Materials Abstracts</collection><collection>Materials Business File</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Neurosciences Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Aerospace Database</collection><collection>Materials Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Biotechnology and BioEngineering Abstracts</collection><collection>MEDLINE - Academic</collection><jtitle>IEEE transaction on neural networks and learning systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Aimar, Alessandro</au><au>Mostafa, Hesham</au><au>Calabrese, Enrico</au><au>Rios-Navarro, Antonio</au><au>Tapiador-Morales, Ricardo</au><au>Lungu, Iulia-Alexandra</au><au>Milde, Moritz B.</au><au>Corradi, Federico</au><au>Linares-Barranco, Alejandro</au><au>Liu, Shih-Chii</au><au>Delbruck, Tobi</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps</atitle><jtitle>IEEE transaction on neural networks and learning systems</jtitle><stitle>TNNLS</stitle><addtitle>IEEE Trans Neural Netw Learn Syst</addtitle><date>2019-03-01</date><risdate>2019</risdate><volume>30</volume><issue>3</issue><spage>644</spage><epage>656</epage><pages>644-656</pages><issn>2162-237X</issn><eissn>2162-2388</eissn><coden>ITNNAL</coden><abstract><![CDATA[Convolutional neural networks (CNNs) have become the dominant neural network architecture for solving many state-of-the-art (SOA) visual processing tasks. Even though graphical processing units are most often used in training and deploying CNNs, their power efficiency is less than 10 GOp/s/W for single-frame runtime inference. We propose a flexible and efficient CNN accelerator architecture called NullHop that implements SOA CNNs useful for low-power and low-latency application scenarios. NullHop exploits the sparsity of neuron activations in CNNs to accelerate the computation and reduce memory requirements. The flexible architecture allows high utilization of available computing resources across kernel sizes ranging from <inline-formula> <tex-math notation="LaTeX">1\times 1 </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">7\times 7 </tex-math></inline-formula>. NullHop can process up to 128 input and 128 output feature maps per layer in a single pass. We implemented the proposed architecture on a Xilinx Zynq field-programmable gate array (FPGA) platform and presented the results showing how our implementation reduces external memory transfers and compute time in five different CNNs ranging from small ones up to the widely known large VGG16 and VGG19 CNNs. Postsynthesis simulations using Mentor Modelsim in a 28-nm process with a clock frequency of 500 MHz show that the VGG19 network achieves over 450 GOp/s. By exploiting sparsity, NullHop achieves an efficiency of 368%, maintains over 98% utilization of the multiply-accumulate units, and achieves a power efficiency of over 3 TOp/s/W in a core area of 6.3 mm 2 . As further proof of NullHop's usability, we interfaced its FPGA implementation with a neuromorphic event camera for real-time interactive demonstrations.]]></abstract><cop>United States</cop><pub>IEEE</pub><pmid>30047912</pmid><doi>10.1109/TNNLS.2018.2852335</doi><tpages>13</tpages><orcidid>https://orcid.org/0000-0002-7268-2915</orcidid><orcidid>https://orcid.org/0000-0001-8667-023X</orcidid><orcidid>https://orcid.org/0000-0001-5479-1141</orcidid><orcidid>https://orcid.org/0000-0002-6056-740X</orcidid><orcidid>https://orcid.org/0000-0002-4517-7382</orcidid><orcidid>https://orcid.org/0000-0003-3594-4960</orcidid><orcidid>https://orcid.org/0000-0003-4163-8484</orcidid><orcidid>https://orcid.org/0000-0002-7557-045X</orcidid><oa>free_for_read</oa></addata></record> |
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subjects | Artificial intelligence Artificial neural networks Computer architecture Computer memory Computer simulation computer vision convolutional neural networks (CNNs) Efficiency Feature extraction Feature maps Field programmable gate arrays field-programmable gate array (FPGA) Graphics processing units Hardware Information processing Kernel Latency Neural networks Pipelines Power efficiency Sparsity State of the art Training Visual tasks VLSI |
title | NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps |
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