Design and characterization of a p+/n-well SPAD array in 150nm CMOS process: erratum

Design and characterization of a p+/n-well SPAD array in 150nm CMOS process: erratum

An erratum is presented to correct a reference mistake in Table 1 in Sect. 4 of [Opt. Express25, 12765 (2017)].

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Veröffentlicht in:Optics express 2017-08, Vol.25 (16), p.19083-19083
Hauptverfasser: Xu, Hesong, Pancheri, Lucio, Betta, Gian-Franco Dalla, Stoppa, David
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creator Xu, Hesong
Pancheri, Lucio
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Stoppa, David
description An erratum is presented to correct a reference mistake in Table 1 in Sect. 4 of [Opt. Express25, 12765 (2017)].
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title Design and characterization of a p+/n-well SPAD array in 150nm CMOS process: erratum
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