Design and Reliability Assessment of Novel 3D-IC Packaging
Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-c...
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Veröffentlicht in: | Journal of mechanics 2017-04, Vol.33 (2), p.193-203 |
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creator | Su, Y.-F. Chiang, K.-N. Liang, Steven Y. |
description | Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry. |
doi_str_mv | 10.1017/jmech.2016.82 |
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fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1904220179</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><cupid>10_1017_jmech_2016_82</cupid><sourcerecordid>1904220179</sourcerecordid><originalsourceid>FETCH-LOGICAL-c443t-a575b9c1e3c9db593b600101d7bcd0e314325e3227796a2b37fc131aa975bd853</originalsourceid><addsrcrecordid>eNptkL1PwzAQxS0EElXpyB6JhSWtz05im61q-ahUAUIwW45zKS75KHGK1P8el3ZAiFvuht97evcIuQQ6Bgpisq7Rvo8ZhWws2QkZgASIJYPsNNyCiViAgnMy8n5NwySKSp4OyM0cvVs1kWmK6AUrZ3JXuX4XTb1H72ts-qgto8f2C6uIz-PFLHo29sOsXLO6IGelqTyOjntI3u5uX2cP8fLpfjGbLmObJLyPTSrSXFlAblWRp4rnGaUhciFyW1DkkHCWImdMCJUZlnNRWuBgjAq6QqZ8SK4Pvpuu_dyi73XtvMWqMg22W69B0YSFx4UK6NUfdN1uuyak0yBlkmWMUhGo-EDZrvW-w1JvOlebbqeB6n2Z-qdMvS9TSxb4yZE3dd65YoW_bP9VfAP4pHR-</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1884662007</pqid></control><display><type>article</type><title>Design and Reliability Assessment of Novel 3D-IC Packaging</title><source>Oxford Journals Open Access Collection</source><source>EZB-FREE-00999 freely available EZB journals</source><source>Cambridge University Press Journals Complete</source><creator>Su, Y.-F. ; Chiang, K.-N. ; Liang, Steven Y.</creator><creatorcontrib>Su, Y.-F. ; Chiang, K.-N. ; Liang, Steven Y.</creatorcontrib><description>Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.</description><identifier>ISSN: 1727-7191</identifier><identifier>EISSN: 1811-8216</identifier><identifier>DOI: 10.1017/jmech.2016.82</identifier><language>eng</language><publisher>Cambridge, UK: Cambridge University Press</publisher><subject>Circuit boards ; Electronics packaging ; Finite element analysis ; Materials selection ; Mechanics ; Microelectronics ; Moore's law ; Packaging ; Reliability analysis ; Soldering ; Solders ; Studies ; Thermal expansion</subject><ispartof>Journal of mechanics, 2017-04, Vol.33 (2), p.193-203</ispartof><rights>Copyright © The Society of Theoretical and Applied Mechanics 2017</rights><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c443t-a575b9c1e3c9db593b600101d7bcd0e314325e3227796a2b37fc131aa975bd853</citedby><cites>FETCH-LOGICAL-c443t-a575b9c1e3c9db593b600101d7bcd0e314325e3227796a2b37fc131aa975bd853</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.cambridge.org/core/product/identifier/S1727719116000824/type/journal_article$$EHTML$$P50$$Gcambridge$$H</linktohtml><link.rule.ids>164,314,780,784,27923,27924,55627</link.rule.ids></links><search><creatorcontrib>Su, Y.-F.</creatorcontrib><creatorcontrib>Chiang, K.-N.</creatorcontrib><creatorcontrib>Liang, Steven Y.</creatorcontrib><title>Design and Reliability Assessment of Novel 3D-IC Packaging</title><title>Journal of mechanics</title><addtitle>J. mech</addtitle><description>Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.</description><subject>Circuit boards</subject><subject>Electronics packaging</subject><subject>Finite element analysis</subject><subject>Materials selection</subject><subject>Mechanics</subject><subject>Microelectronics</subject><subject>Moore's law</subject><subject>Packaging</subject><subject>Reliability analysis</subject><subject>Soldering</subject><subject>Solders</subject><subject>Studies</subject><subject>Thermal expansion</subject><issn>1727-7191</issn><issn>1811-8216</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><sourceid>ABUWG</sourceid><sourceid>AFKRA</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><recordid>eNptkL1PwzAQxS0EElXpyB6JhSWtz05im61q-ahUAUIwW45zKS75KHGK1P8el3ZAiFvuht97evcIuQQ6Bgpisq7Rvo8ZhWws2QkZgASIJYPsNNyCiViAgnMy8n5NwySKSp4OyM0cvVs1kWmK6AUrZ3JXuX4XTb1H72ts-qgto8f2C6uIz-PFLHo29sOsXLO6IGelqTyOjntI3u5uX2cP8fLpfjGbLmObJLyPTSrSXFlAblWRp4rnGaUhciFyW1DkkHCWImdMCJUZlnNRWuBgjAq6QqZ8SK4Pvpuu_dyi73XtvMWqMg22W69B0YSFx4UK6NUfdN1uuyak0yBlkmWMUhGo-EDZrvW-w1JvOlebbqeB6n2Z-qdMvS9TSxb4yZE3dd65YoW_bP9VfAP4pHR-</recordid><startdate>20170401</startdate><enddate>20170401</enddate><creator>Su, Y.-F.</creator><creator>Chiang, K.-N.</creator><creator>Liang, Steven Y.</creator><general>Cambridge University Press</general><general>Oxford University Press</general><scope>AAYXX</scope><scope>CITATION</scope><scope>3V.</scope><scope>7TB</scope><scope>7WY</scope><scope>7WZ</scope><scope>7XB</scope><scope>87Z</scope><scope>8FD</scope><scope>8FE</scope><scope>8FG</scope><scope>8FK</scope><scope>8FL</scope><scope>ABJCF</scope><scope>ABUWG</scope><scope>AFKRA</scope><scope>BENPR</scope><scope>BEZIV</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>FR3</scope><scope>FRNLG</scope><scope>F~G</scope><scope>HCIFZ</scope><scope>K60</scope><scope>K6~</scope><scope>KR7</scope><scope>L.-</scope><scope>L6V</scope><scope>M0C</scope><scope>M7S</scope><scope>PQBIZ</scope><scope>PQBZA</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PTHSS</scope><scope>Q9U</scope><scope>S0W</scope></search><sort><creationdate>20170401</creationdate><title>Design and Reliability Assessment of Novel 3D-IC Packaging</title><author>Su, Y.-F. ; Chiang, K.-N. ; Liang, Steven Y.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c443t-a575b9c1e3c9db593b600101d7bcd0e314325e3227796a2b37fc131aa975bd853</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>Circuit boards</topic><topic>Electronics packaging</topic><topic>Finite element analysis</topic><topic>Materials selection</topic><topic>Mechanics</topic><topic>Microelectronics</topic><topic>Moore's law</topic><topic>Packaging</topic><topic>Reliability analysis</topic><topic>Soldering</topic><topic>Solders</topic><topic>Studies</topic><topic>Thermal expansion</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Su, Y.-F.</creatorcontrib><creatorcontrib>Chiang, K.-N.</creatorcontrib><creatorcontrib>Liang, Steven Y.</creatorcontrib><collection>CrossRef</collection><collection>ProQuest Central (Corporate)</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>ABI/INFORM Collection</collection><collection>ABI/INFORM Global (PDF only)</collection><collection>ProQuest Central (purchase pre-March 2016)</collection><collection>ABI/INFORM Global (Alumni Edition)</collection><collection>Technology Research Database</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>ProQuest Central (Alumni) (purchase pre-March 2016)</collection><collection>ABI/INFORM Collection (Alumni Edition)</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central (Alumni Edition)</collection><collection>ProQuest Central UK/Ireland</collection><collection>ProQuest Central</collection><collection>Business Premium Collection</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>Engineering Research Database</collection><collection>Business Premium Collection (Alumni)</collection><collection>ABI/INFORM Global (Corporate)</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Business Collection (Alumni Edition)</collection><collection>ProQuest Business Collection</collection><collection>Civil Engineering Abstracts</collection><collection>ABI/INFORM Professional Advanced</collection><collection>ProQuest Engineering Collection</collection><collection>ABI/INFORM Global</collection><collection>Engineering Database</collection><collection>ProQuest One Business</collection><collection>ProQuest One Business (Alumni)</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>Engineering Collection</collection><collection>ProQuest Central Basic</collection><collection>DELNET Engineering & Technology Collection</collection><jtitle>Journal of mechanics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Su, Y.-F.</au><au>Chiang, K.-N.</au><au>Liang, Steven Y.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Design and Reliability Assessment of Novel 3D-IC Packaging</atitle><jtitle>Journal of mechanics</jtitle><addtitle>J. mech</addtitle><date>2017-04-01</date><risdate>2017</risdate><volume>33</volume><issue>2</issue><spage>193</spage><epage>203</epage><pages>193-203</pages><issn>1727-7191</issn><eissn>1811-8216</eissn><abstract>Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.</abstract><cop>Cambridge, UK</cop><pub>Cambridge University Press</pub><doi>10.1017/jmech.2016.82</doi><tpages>11</tpages><oa>free_for_read</oa></addata></record> |
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subjects | Circuit boards Electronics packaging Finite element analysis Materials selection Mechanics Microelectronics Moore's law Packaging Reliability analysis Soldering Solders Studies Thermal expansion |
title | Design and Reliability Assessment of Novel 3D-IC Packaging |
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