Design and Reliability Assessment of Novel 3D-IC Packaging

Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-c...

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Veröffentlicht in:Journal of mechanics 2017-04, Vol.33 (2), p.193-203
Hauptverfasser: Su, Y.-F., Chiang, K.-N., Liang, Steven Y.
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creator Su, Y.-F.
Chiang, K.-N.
Liang, Steven Y.
description Presently, physical limitations are restricting the development of the microelectronic industry driven by Moore's law. To achieve high-performance, small form factor, and lightweight applications, new electronic packaging methods have exceeded Moore's law. This research proposes a double-chip stacking structure in an embedded fan-out wafer-level packaging with double-sided interconnections. The overall reliability of the solder joints and redistributed lines is assessed through finite element analysis. The application of soft lamination material and selection of a carrier material whose coefficient of thermal expansion (CTE) is close to that of the printed circuit board can effectively enhance the reliability of solder joints over more than 1,000 cycles. A trace/pad junction whose direction is parallel to the major direction of the CTE mismatch is recommended, and the curved portion of trace lines can absorb the expansion of metal lines and filler material. Design-on-simulation methodology is necessary to develop novel packaging structures in the electronic packaging industry.
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source Oxford Journals Open Access Collection; EZB-FREE-00999 freely available EZB journals; Cambridge University Press Journals Complete
subjects Circuit boards
Electronics packaging
Finite element analysis
Materials selection
Mechanics
Microelectronics
Moore's law
Packaging
Reliability analysis
Soldering
Solders
Studies
Thermal expansion
title Design and Reliability Assessment of Novel 3D-IC Packaging
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