A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI
An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, wh...
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| Veröffentlicht in: | IEICE Transactions on Electronics 2017/03/01, Vol.E100.C(3), pp.259-267 |
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| container_title | IEICE Transactions on Electronics |
| container_volume | E100.C |
| creator | NARAYANAN, Aravind THARAYIL DENG, Wei YANG, Dongsheng WU, Rui OKADA, Kenichi MATSUZAWA, Akira |
| description | An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply. |
| doi_str_mv | 10.1587/transele.E100.C.259 |
| format | Article |
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The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.</description><identifier>ISSN: 0916-8524</identifier><identifier>EISSN: 1745-1353</identifier><identifier>DOI: 10.1587/transele.E100.C.259</identifier><language>eng</language><publisher>The Institute of Electronics, Information and Communication Engineers</publisher><subject>all-digital ; Architecture ; clock data recovery ; Clocks ; Design engineering ; Design improvements ; Electronics ; fully-synthesizable ; injection locking ; Manuals ; Migration ; phase-filtering ; Power consumption</subject><ispartof>IEICE Transactions on Electronics, 2017/03/01, Vol.E100.C(3), pp.259-267</ispartof><rights>2017 The Institute of Electronics, Information and Communication Engineers</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c560t-1d0774b174db505bd89fde30adadb2f384d2410becf9164c54a74329ad3c2d333</citedby><cites>FETCH-LOGICAL-c560t-1d0774b174db505bd89fde30adadb2f384d2410becf9164c54a74329ad3c2d333</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,1881,27923,27924</link.rule.ids></links><search><creatorcontrib>NARAYANAN, Aravind THARAYIL</creatorcontrib><creatorcontrib>DENG, Wei</creatorcontrib><creatorcontrib>YANG, Dongsheng</creatorcontrib><creatorcontrib>WU, Rui</creatorcontrib><creatorcontrib>OKADA, Kenichi</creatorcontrib><creatorcontrib>MATSUZAWA, Akira</creatorcontrib><title>A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI</title><title>IEICE Transactions on Electronics</title><addtitle>IEICE Trans. Electron.</addtitle><description>An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. The system achieves a maximum data rate of 10.06Gbps while consuming a power of 16.1mW from a 1V power supply.</description><subject>all-digital</subject><subject>Architecture</subject><subject>clock data recovery</subject><subject>Clocks</subject><subject>Design engineering</subject><subject>Design improvements</subject><subject>Electronics</subject><subject>fully-synthesizable</subject><subject>injection locking</subject><subject>Manuals</subject><subject>Migration</subject><subject>phase-filtering</subject><subject>Power consumption</subject><issn>0916-8524</issn><issn>1745-1353</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2017</creationdate><recordtype>article</recordtype><recordid>eNpdkDtPwzAURi0EEqXwC1g8siT4mThjlT4IqlSJghgtx3ZoSuIUOx3KrydVASGmu5zz6eoAcItRjLlI73uvXLCNjWcYoTiPCc_OwAinjEeYcnoORijDSSQ4YZfgKoQtQlgQTEegmMD5vmkO0frg-o0N9acqGwuHYZQsyl2AOIlx-woLt7W6rzsXLTv9bg3Mp0-wdpAI18L5dL0qrsFFpZpgb77vGLzMZ8_5Q7RcLYp8sow0T1AfYYPSlJXDb6bkiJdGZJWxFCmjTEkqKpghDKPS6mp4mWnOVMooyZShmhhK6RjcnXZ3vvvY29DLtg7aNo1yttsHiUVGhSAcowGlJ1T7LgRvK7nzdav8QWIkj-HkTzh5DCdzOYQbrMeTtQ29erO_jvJ9rQf0v0P_yL-Q3igvraNfUwR7Sw</recordid><startdate>20170101</startdate><enddate>20170101</enddate><creator>NARAYANAN, Aravind THARAYIL</creator><creator>DENG, Wei</creator><creator>YANG, Dongsheng</creator><creator>WU, Rui</creator><creator>OKADA, Kenichi</creator><creator>MATSUZAWA, Akira</creator><general>The Institute of Electronics, Information and Communication Engineers</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20170101</creationdate><title>A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI</title><author>NARAYANAN, Aravind THARAYIL ; DENG, Wei ; YANG, Dongsheng ; WU, Rui ; OKADA, Kenichi ; MATSUZAWA, Akira</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c560t-1d0774b174db505bd89fde30adadb2f384d2410becf9164c54a74329ad3c2d333</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2017</creationdate><topic>all-digital</topic><topic>Architecture</topic><topic>clock data recovery</topic><topic>Clocks</topic><topic>Design engineering</topic><topic>Design improvements</topic><topic>Electronics</topic><topic>fully-synthesizable</topic><topic>injection locking</topic><topic>Manuals</topic><topic>Migration</topic><topic>phase-filtering</topic><topic>Power consumption</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>NARAYANAN, Aravind THARAYIL</creatorcontrib><creatorcontrib>DENG, Wei</creatorcontrib><creatorcontrib>YANG, Dongsheng</creatorcontrib><creatorcontrib>WU, Rui</creatorcontrib><creatorcontrib>OKADA, Kenichi</creatorcontrib><creatorcontrib>MATSUZAWA, Akira</creatorcontrib><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEICE Transactions on Electronics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>NARAYANAN, Aravind THARAYIL</au><au>DENG, Wei</au><au>YANG, Dongsheng</au><au>WU, Rui</au><au>OKADA, Kenichi</au><au>MATSUZAWA, Akira</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI</atitle><jtitle>IEICE Transactions on Electronics</jtitle><addtitle>IEICE Trans. Electron.</addtitle><date>2017-01-01</date><risdate>2017</risdate><volume>E100.C</volume><issue>3</issue><spage>259</spage><epage>267</epage><pages>259-267</pages><issn>0916-8524</issn><eissn>1745-1353</eissn><abstract>An all-digital fully-synthesizable PVT-tolerant clock data recovery (CDR) architecture for wireline chip-to-chip interconnects is presented. The proposed architecture enables the co-synthesis of the CDR with the digital core. By eliminating the resource hungry manual layout and interfacing steps, which are necessary for conventional CDR topologies, the design process and the time-to-market can be drastically improved. Besides, the proposed CDR architecture enables the re-usability of majority of the sub-systems which enables easy migration to different process nodes. The proposed CDR is also equipped with a self-calibration scheme for ensuring tolerence over PVT. The proposed fully-syntehsizable CDR was implemented in 28nm FDSOI. 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| language | eng |
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| source | J-STAGE Free |
| subjects | all-digital Architecture clock data recovery Clocks Design engineering Design improvements Electronics fully-synthesizable injection locking Manuals Migration phase-filtering Power consumption |
| title | A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI |
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