Trivium hardware implementations for power reduction

Summary This paper describes the use of parallelization techniques to reduce dynamic power consumption in hardware implementations of the Trivium stream cipher. Trivium is a synchronous stream cipher based on a combination of three non‐linear feedback shift registers. In 2008, it was chosen as a fin...

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Veröffentlicht in:	International journal of circuit theory and applications 2017-02, Vol.45 (2), p.188-198
Hauptverfasser:	Mora‐Gutiérrez, J. M., Jiménez‐Fernández, C.J., Valencia‐Barrero, M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Computer simulation Design standards Encryption Hardware hardware implementation lightweight cryptography low power Power consumption Semiconductor devices stream cipher Transistors Trivium
Online-Zugang:	Volltext
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