Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs
In this paper we investigate the effects of asymmetric organization and depths of Network-on-Chip (NoC) router buffers among dies in heterogeneous 3D-System-on-Chips (SoCs). In our novel approach the properties of the routers are aligned with the characteristics of the technological nodes per layer....
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| Veröffentlicht in: | Microprocessors and microsystems 2017-02, Vol.48, p.36-47 |
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| container_title | Microprocessors and microsystems |
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| creator | Joseph, Jan Moritz Blochwitz, Christopher García-Ortiz, Alberto Pionteck, Thilo |
| description | In this paper we investigate the effects of asymmetric organization and depths of Network-on-Chip (NoC) router buffers among dies in heterogeneous 3D-System-on-Chips (SoCs). In our novel approach the properties of the routers are aligned with the characteristics of the technological nodes per layer. We call these designs Asymmetric 3D-NoCs (A-3D-NoCs). In this work we demonstrate potentials of A-3D-NoCs in comparison to a conventional, symmetric 3D-NoC: Applying asymmetric buffer reorganization we achieve area savings of 8.3% and power savings of 5.4% for link buffers while accepting a minor average system performance loss of 2.1%. With additional asymmetry in buffer depth up to 28% cost savings and 15% power reduction are given in combination with a 4.6% performance decline. Thus, the proposed buffer organization scheme is applicable for cost and power critical applications of NoCs in heterogeneous 3D-SoCs. |
| doi_str_mv | 10.1016/j.micpro.2016.09.011 |
| format | Article |
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| identifier | ISSN: 0141-9331 |
| ispartof | Microprocessors and microsystems, 2017-02, Vol.48, p.36-47 |
| issn | 0141-9331 1872-9436 |
| language | eng |
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| source | Elsevier ScienceDirect Journals |
| subjects | Asymmetric 3D-Noc Asymmetry Buffer depths Buffer reorganization Buffers Cost engineering Design engineering Dies Energy conservation Heterogeneous 3D-System-on-Chip Integrated circuits Microprocessors Network-on-Chip Networks Organizations Routers System on chip |
| title | Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs |
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