Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs
This research studies the effects of post-metal deposition annealing temperature on degradation induced by positive bias stress (PBS) in TiN/HfO2 n-channel fin field-effect transistors (FinFETs). The initial electrical characteristics possess higher threshold voltage, transconductance and on-state c...
Gespeichert in:
| Veröffentlicht in: | Thin solid films 2016-12, Vol.620, p.30-33 |
|---|---|
| Hauptverfasser: | , , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 33 |
|---|---|
| container_issue | |
| container_start_page | 30 |
| container_title | Thin solid films |
| container_volume | 620 |
| creator | Lin, Chien-Yu Chang, Ting-Chang Liu, Kuan-Ju Tsai, Jyun-Yu Chen, Ching-En Liu, Hsi-Wen Lu, Ying-Hsin Tseng, Tseung-Yuen Cheng, Osbert Huang, Cheng-Tung |
| description | This research studies the effects of post-metal deposition annealing temperature on degradation induced by positive bias stress (PBS) in TiN/HfO2 n-channel fin field-effect transistors (FinFETs). The initial electrical characteristics possess higher threshold voltage, transconductance and on-state current in high-annealing temperature devices. In addition, PBS-induced degradation was found to be more severe in high-annealing temperature devices due to more high-k bulk traps. However, in these devices, oxygen vacancies are generated within HfO2 since oxygen is more likely to diffuse toward the interface layer (IL) and repair Si/SiO2 dangling bonds. Furthermore, using charge-pumping and C–V measurements, less interface trapping and a thicker IL were found in high-annealing temperature devices, verifying the proposed model.
•Oxygen diffusion affects device performance.•Dipoles are induced in the HfO2/SiO2 interface.•Dipole leads to Vth shift. |
| doi_str_mv | 10.1016/j.tsf.2016.08.072 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1864529351</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0040609016305533</els_id><sourcerecordid>1864529351</sourcerecordid><originalsourceid>FETCH-LOGICAL-c330t-e20c37e87e34a62bf9758ec16021d038fa237287345f41193458c4a0c3e3e3e63</originalsourceid><addsrcrecordid>eNp9kMtOwzAQRS0EEqXwAey8ZOMwttPEEStU8aioxAbWlutMWld5YbtI_XscyhrNYmY8917Jh5BbDhkHXtzvsxiaTKQxA5VBKc7IjKuyYqKU_JzMAHJgBVRwSa5C2AMAF0LOSFh1o7GRDg0dhxBZh9G0tMa0uOiGnpq-R9O6fksjdiN6Ew8eaTqkuRl8Z3qLSVRTj60zG9e6eJzSdm67Y2_0N49tTUTas2fXPz99hGty0Zg24M1fn5PP9Lx8Zev3l9Xycc2slBAZCrCyRFWizE0hNk1VLhRaXoDgNUjVGCFLoUqZL5qc8yp1ZXOTTDhVIefk7pQ7-uHrgCHqzgWLbWt6HA5Bc1XkC1HJBU9SfpJaP4TgsdGjd53xR81BT4D1XifAegKsQekEOHkeTh5Mf_h26HWwDhOO2nm0UdeD-8f9A-X8g8w</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1864529351</pqid></control><display><type>article</type><title>Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs</title><source>ScienceDirect Journals (5 years ago - present)</source><creator>Lin, Chien-Yu ; Chang, Ting-Chang ; Liu, Kuan-Ju ; Tsai, Jyun-Yu ; Chen, Ching-En ; Liu, Hsi-Wen ; Lu, Ying-Hsin ; Tseng, Tseung-Yuen ; Cheng, Osbert ; Huang, Cheng-Tung</creator><creatorcontrib>Lin, Chien-Yu ; Chang, Ting-Chang ; Liu, Kuan-Ju ; Tsai, Jyun-Yu ; Chen, Ching-En ; Liu, Hsi-Wen ; Lu, Ying-Hsin ; Tseng, Tseung-Yuen ; Cheng, Osbert ; Huang, Cheng-Tung</creatorcontrib><description>This research studies the effects of post-metal deposition annealing temperature on degradation induced by positive bias stress (PBS) in TiN/HfO2 n-channel fin field-effect transistors (FinFETs). The initial electrical characteristics possess higher threshold voltage, transconductance and on-state current in high-annealing temperature devices. In addition, PBS-induced degradation was found to be more severe in high-annealing temperature devices due to more high-k bulk traps. However, in these devices, oxygen vacancies are generated within HfO2 since oxygen is more likely to diffuse toward the interface layer (IL) and repair Si/SiO2 dangling bonds. Furthermore, using charge-pumping and C–V measurements, less interface trapping and a thicker IL were found in high-annealing temperature devices, verifying the proposed model.
•Oxygen diffusion affects device performance.•Dipoles are induced in the HfO2/SiO2 interface.•Dipole leads to Vth shift.</description><identifier>ISSN: 0040-6090</identifier><identifier>EISSN: 1879-2731</identifier><identifier>DOI: 10.1016/j.tsf.2016.08.072</identifier><language>eng</language><publisher>Elsevier B.V</publisher><subject>Annealing ; Degradation ; Deposition ; Devices ; FinFET ; Hafnium oxide ; High-k/metal gate ; n-MOSFETs ; Oxygen ; PBTI ; Threshold voltage ; Trapping</subject><ispartof>Thin solid films, 2016-12, Vol.620, p.30-33</ispartof><rights>2016 Elsevier B.V.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c330t-e20c37e87e34a62bf9758ec16021d038fa237287345f41193458c4a0c3e3e3e63</citedby><cites>FETCH-LOGICAL-c330t-e20c37e87e34a62bf9758ec16021d038fa237287345f41193458c4a0c3e3e3e63</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://dx.doi.org/10.1016/j.tsf.2016.08.072$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,780,784,3550,27924,27925,45995</link.rule.ids></links><search><creatorcontrib>Lin, Chien-Yu</creatorcontrib><creatorcontrib>Chang, Ting-Chang</creatorcontrib><creatorcontrib>Liu, Kuan-Ju</creatorcontrib><creatorcontrib>Tsai, Jyun-Yu</creatorcontrib><creatorcontrib>Chen, Ching-En</creatorcontrib><creatorcontrib>Liu, Hsi-Wen</creatorcontrib><creatorcontrib>Lu, Ying-Hsin</creatorcontrib><creatorcontrib>Tseng, Tseung-Yuen</creatorcontrib><creatorcontrib>Cheng, Osbert</creatorcontrib><creatorcontrib>Huang, Cheng-Tung</creatorcontrib><title>Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs</title><title>Thin solid films</title><description>This research studies the effects of post-metal deposition annealing temperature on degradation induced by positive bias stress (PBS) in TiN/HfO2 n-channel fin field-effect transistors (FinFETs). The initial electrical characteristics possess higher threshold voltage, transconductance and on-state current in high-annealing temperature devices. In addition, PBS-induced degradation was found to be more severe in high-annealing temperature devices due to more high-k bulk traps. However, in these devices, oxygen vacancies are generated within HfO2 since oxygen is more likely to diffuse toward the interface layer (IL) and repair Si/SiO2 dangling bonds. Furthermore, using charge-pumping and C–V measurements, less interface trapping and a thicker IL were found in high-annealing temperature devices, verifying the proposed model.
•Oxygen diffusion affects device performance.•Dipoles are induced in the HfO2/SiO2 interface.•Dipole leads to Vth shift.</description><subject>Annealing</subject><subject>Degradation</subject><subject>Deposition</subject><subject>Devices</subject><subject>FinFET</subject><subject>Hafnium oxide</subject><subject>High-k/metal gate</subject><subject>n-MOSFETs</subject><subject>Oxygen</subject><subject>PBTI</subject><subject>Threshold voltage</subject><subject>Trapping</subject><issn>0040-6090</issn><issn>1879-2731</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2016</creationdate><recordtype>article</recordtype><recordid>eNp9kMtOwzAQRS0EEqXwAey8ZOMwttPEEStU8aioxAbWlutMWld5YbtI_XscyhrNYmY8917Jh5BbDhkHXtzvsxiaTKQxA5VBKc7IjKuyYqKU_JzMAHJgBVRwSa5C2AMAF0LOSFh1o7GRDg0dhxBZh9G0tMa0uOiGnpq-R9O6fksjdiN6Ew8eaTqkuRl8Z3qLSVRTj60zG9e6eJzSdm67Y2_0N49tTUTas2fXPz99hGty0Zg24M1fn5PP9Lx8Zev3l9Xycc2slBAZCrCyRFWizE0hNk1VLhRaXoDgNUjVGCFLoUqZL5qc8yp1ZXOTTDhVIefk7pQ7-uHrgCHqzgWLbWt6HA5Bc1XkC1HJBU9SfpJaP4TgsdGjd53xR81BT4D1XifAegKsQekEOHkeTh5Mf_h26HWwDhOO2nm0UdeD-8f9A-X8g8w</recordid><startdate>20161201</startdate><enddate>20161201</enddate><creator>Lin, Chien-Yu</creator><creator>Chang, Ting-Chang</creator><creator>Liu, Kuan-Ju</creator><creator>Tsai, Jyun-Yu</creator><creator>Chen, Ching-En</creator><creator>Liu, Hsi-Wen</creator><creator>Lu, Ying-Hsin</creator><creator>Tseng, Tseung-Yuen</creator><creator>Cheng, Osbert</creator><creator>Huang, Cheng-Tung</creator><general>Elsevier B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SR</scope><scope>7U5</scope><scope>8BQ</scope><scope>8FD</scope><scope>JG9</scope><scope>L7M</scope></search><sort><creationdate>20161201</creationdate><title>Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs</title><author>Lin, Chien-Yu ; Chang, Ting-Chang ; Liu, Kuan-Ju ; Tsai, Jyun-Yu ; Chen, Ching-En ; Liu, Hsi-Wen ; Lu, Ying-Hsin ; Tseng, Tseung-Yuen ; Cheng, Osbert ; Huang, Cheng-Tung</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c330t-e20c37e87e34a62bf9758ec16021d038fa237287345f41193458c4a0c3e3e3e63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2016</creationdate><topic>Annealing</topic><topic>Degradation</topic><topic>Deposition</topic><topic>Devices</topic><topic>FinFET</topic><topic>Hafnium oxide</topic><topic>High-k/metal gate</topic><topic>n-MOSFETs</topic><topic>Oxygen</topic><topic>PBTI</topic><topic>Threshold voltage</topic><topic>Trapping</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Lin, Chien-Yu</creatorcontrib><creatorcontrib>Chang, Ting-Chang</creatorcontrib><creatorcontrib>Liu, Kuan-Ju</creatorcontrib><creatorcontrib>Tsai, Jyun-Yu</creatorcontrib><creatorcontrib>Chen, Ching-En</creatorcontrib><creatorcontrib>Liu, Hsi-Wen</creatorcontrib><creatorcontrib>Lu, Ying-Hsin</creatorcontrib><creatorcontrib>Tseng, Tseung-Yuen</creatorcontrib><creatorcontrib>Cheng, Osbert</creatorcontrib><creatorcontrib>Huang, Cheng-Tung</creatorcontrib><collection>CrossRef</collection><collection>Engineered Materials Abstracts</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>METADEX</collection><collection>Technology Research Database</collection><collection>Materials Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Thin solid films</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Lin, Chien-Yu</au><au>Chang, Ting-Chang</au><au>Liu, Kuan-Ju</au><au>Tsai, Jyun-Yu</au><au>Chen, Ching-En</au><au>Liu, Hsi-Wen</au><au>Lu, Ying-Hsin</au><au>Tseng, Tseung-Yuen</au><au>Cheng, Osbert</au><au>Huang, Cheng-Tung</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs</atitle><jtitle>Thin solid films</jtitle><date>2016-12-01</date><risdate>2016</risdate><volume>620</volume><spage>30</spage><epage>33</epage><pages>30-33</pages><issn>0040-6090</issn><eissn>1879-2731</eissn><abstract>This research studies the effects of post-metal deposition annealing temperature on degradation induced by positive bias stress (PBS) in TiN/HfO2 n-channel fin field-effect transistors (FinFETs). The initial electrical characteristics possess higher threshold voltage, transconductance and on-state current in high-annealing temperature devices. In addition, PBS-induced degradation was found to be more severe in high-annealing temperature devices due to more high-k bulk traps. However, in these devices, oxygen vacancies are generated within HfO2 since oxygen is more likely to diffuse toward the interface layer (IL) and repair Si/SiO2 dangling bonds. Furthermore, using charge-pumping and C–V measurements, less interface trapping and a thicker IL were found in high-annealing temperature devices, verifying the proposed model.
•Oxygen diffusion affects device performance.•Dipoles are induced in the HfO2/SiO2 interface.•Dipole leads to Vth shift.</abstract><pub>Elsevier B.V</pub><doi>10.1016/j.tsf.2016.08.072</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0040-6090 |
| ispartof | Thin solid films, 2016-12, Vol.620, p.30-33 |
| issn | 0040-6090 1879-2731 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_1864529351 |
| source | ScienceDirect Journals (5 years ago - present) |
| subjects | Annealing Degradation Deposition Devices FinFET Hafnium oxide High-k/metal gate n-MOSFETs Oxygen PBTI Threshold voltage Trapping |
| title | Impact of post-metal deposition annealing temperature on performance and reliability of high-K metal-gate n-FinFETs |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-06T09%3A04%3A21IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Impact%20of%20post-metal%20deposition%20annealing%20temperature%20on%20performance%20and%20reliability%20of%20high-K%20metal-gate%20n-FinFETs&rft.jtitle=Thin%20solid%20films&rft.au=Lin,%20Chien-Yu&rft.date=2016-12-01&rft.volume=620&rft.spage=30&rft.epage=33&rft.pages=30-33&rft.issn=0040-6090&rft.eissn=1879-2731&rft_id=info:doi/10.1016/j.tsf.2016.08.072&rft_dat=%3Cproquest_cross%3E1864529351%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1864529351&rft_id=info:pmid/&rft_els_id=S0040609016305533&rfr_iscdi=true |