At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems
Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the reference voltage level (Vref) in the receiver. The trad...
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| creator | Mukherjee, S. Chandrasekaran, S. Subramanyan, E. K. Ganapathy Sendhil, A. |
| description | Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the reference voltage level (Vref) in the receiver. The traditional method to choose Vref is to sweep the reference voltage level while performing a link Bit Error Rate (BER) test. This existing method has serious disadvantages like additional circuitry, system overhead and a very long time to completion. In this paper, a fast technique to obtain optimum value of Vref is proposed. It uses a simple density test at the receiver to perform the operation. This technique has been demonstrated in a POD (Pseudo Open-Drain) signaling based single-ended transceiver designed in TSMC 40nm process. System level measurements in the lab at 6 Gb/s data rate prove that this technique is as accurate as the traditional technique in choosing Vref while being several thousand times faster. |
| doi_str_mv | 10.1109/VLSID.2013.204 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_proquest_miscellaneous_1837316677</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6472656</ieee_id><sourcerecordid>1837316677</sourcerecordid><originalsourceid>FETCH-LOGICAL-i241t-5e3eae4dbde85a0c2baaa07c56789d40f23d6e561b9c4e54c878177a99674d43</originalsourceid><addsrcrecordid>eNqFjztPw0AQhI-XRBLS0tBcSePkXt67KyMgJFJQCkcRnXWx1-GQH8HnFOHXYxF6mt0Z6dvRLCH3nE04Z3a6XSXL54lgXPZDXZCx1YZpsLEyxrJLMhDSsAiskFdkyBVoqUDa92sy4AxkZAH0LRmG8MkYMzHTA7KddVE4IOZ0OV3TDYaOFk1L564X2xYLuj50vvLfrvNNTX1NF37_QZPfi8TX-xIjrPPevGHVtCeanEKHVbgjN4UrA47_9ohs5i-bp0W0Wr8un2aryAvFuyhGiQ5VvsvRxI5lYuecYzqLQRubK1YImQPGwHc2UxirzGjDtXbWgla5kiPyeI49tM3XsS-fVj5kWJauxuYYUm6klrz_Wv-PagOizwbo0Ycz6hExPbS-cu0pBaUFxCB_AOfRb1s</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>1786217766</pqid></control><display><type>conference_proceeding</type><title>At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Mukherjee, S. ; Chandrasekaran, S. ; Subramanyan, E. K. Ganapathy ; Sendhil, A.</creator><creatorcontrib>Mukherjee, S. ; Chandrasekaran, S. ; Subramanyan, E. K. Ganapathy ; Sendhil, A.</creatorcontrib><description>Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the reference voltage level (Vref) in the receiver. The traditional method to choose Vref is to sweep the reference voltage level while performing a link Bit Error Rate (BER) test. This existing method has serious disadvantages like additional circuitry, system overhead and a very long time to completion. In this paper, a fast technique to obtain optimum value of Vref is proposed. It uses a simple density test at the receiver to perform the operation. This technique has been demonstrated in a POD (Pseudo Open-Drain) signaling based single-ended transceiver designed in TSMC 40nm process. System level measurements in the lab at 6 Gb/s data rate prove that this technique is as accurate as the traditional technique in choosing Vref while being several thousand times faster.</description><identifier>ISSN: 1063-9667</identifier><identifier>ISBN: 146734639X</identifier><identifier>ISBN: 9781467346399</identifier><identifier>EISSN: 2380-6923</identifier><identifier>EISBN: 9780769548890</identifier><identifier>EISBN: 076954889X</identifier><identifier>DOI: 10.1109/VLSID.2013.204</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>BER ; Bit error rate ; Conferences ; Density ; Design engineering ; Electric potential ; Integrated circuits ; memory ; Optimization ; Random access memory ; Receivers ; Reference voltage ; Silicon ; single-ended ; Timing ; Transmitters ; Voltage ; Vref</subject><ispartof>2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013, p.297-301</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6472656$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,777,781,786,787,2052,27905,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6472656$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Mukherjee, S.</creatorcontrib><creatorcontrib>Chandrasekaran, S.</creatorcontrib><creatorcontrib>Subramanyan, E. K. Ganapathy</creatorcontrib><creatorcontrib>Sendhil, A.</creatorcontrib><title>At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems</title><title>2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems</title><addtitle>ICVD</addtitle><description>Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the reference voltage level (Vref) in the receiver. The traditional method to choose Vref is to sweep the reference voltage level while performing a link Bit Error Rate (BER) test. This existing method has serious disadvantages like additional circuitry, system overhead and a very long time to completion. In this paper, a fast technique to obtain optimum value of Vref is proposed. It uses a simple density test at the receiver to perform the operation. This technique has been demonstrated in a POD (Pseudo Open-Drain) signaling based single-ended transceiver designed in TSMC 40nm process. System level measurements in the lab at 6 Gb/s data rate prove that this technique is as accurate as the traditional technique in choosing Vref while being several thousand times faster.</description><subject>BER</subject><subject>Bit error rate</subject><subject>Conferences</subject><subject>Density</subject><subject>Design engineering</subject><subject>Electric potential</subject><subject>Integrated circuits</subject><subject>memory</subject><subject>Optimization</subject><subject>Random access memory</subject><subject>Receivers</subject><subject>Reference voltage</subject><subject>Silicon</subject><subject>single-ended</subject><subject>Timing</subject><subject>Transmitters</subject><subject>Voltage</subject><subject>Vref</subject><issn>1063-9667</issn><issn>2380-6923</issn><isbn>146734639X</isbn><isbn>9781467346399</isbn><isbn>9780769548890</isbn><isbn>076954889X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqFjztPw0AQhI-XRBLS0tBcSePkXt67KyMgJFJQCkcRnXWx1-GQH8HnFOHXYxF6mt0Z6dvRLCH3nE04Z3a6XSXL54lgXPZDXZCx1YZpsLEyxrJLMhDSsAiskFdkyBVoqUDa92sy4AxkZAH0LRmG8MkYMzHTA7KddVE4IOZ0OV3TDYaOFk1L564X2xYLuj50vvLfrvNNTX1NF37_QZPfi8TX-xIjrPPevGHVtCeanEKHVbgjN4UrA47_9ohs5i-bp0W0Wr8un2aryAvFuyhGiQ5VvsvRxI5lYuecYzqLQRubK1YImQPGwHc2UxirzGjDtXbWgla5kiPyeI49tM3XsS-fVj5kWJauxuYYUm6klrz_Wv-PagOizwbo0Ycz6hExPbS-cu0pBaUFxCB_AOfRb1s</recordid><startdate>201301</startdate><enddate>201301</enddate><creator>Mukherjee, S.</creator><creator>Chandrasekaran, S.</creator><creator>Subramanyan, E. K. Ganapathy</creator><creator>Sendhil, A.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>7TK</scope></search><sort><creationdate>201301</creationdate><title>At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems</title><author>Mukherjee, S. ; Chandrasekaran, S. ; Subramanyan, E. K. Ganapathy ; Sendhil, A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i241t-5e3eae4dbde85a0c2baaa07c56789d40f23d6e561b9c4e54c878177a99674d43</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BER</topic><topic>Bit error rate</topic><topic>Conferences</topic><topic>Density</topic><topic>Design engineering</topic><topic>Electric potential</topic><topic>Integrated circuits</topic><topic>memory</topic><topic>Optimization</topic><topic>Random access memory</topic><topic>Receivers</topic><topic>Reference voltage</topic><topic>Silicon</topic><topic>single-ended</topic><topic>Timing</topic><topic>Transmitters</topic><topic>Voltage</topic><topic>Vref</topic><toplevel>online_resources</toplevel><creatorcontrib>Mukherjee, S.</creatorcontrib><creatorcontrib>Chandrasekaran, S.</creatorcontrib><creatorcontrib>Subramanyan, E. K. Ganapathy</creatorcontrib><creatorcontrib>Sendhil, A.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Neurosciences Abstracts</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Mukherjee, S.</au><au>Chandrasekaran, S.</au><au>Subramanyan, E. K. Ganapathy</au><au>Sendhil, A.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems</atitle><btitle>2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems</btitle><stitle>ICVD</stitle><date>2013-01</date><risdate>2013</risdate><spage>297</spage><epage>301</epage><pages>297-301</pages><issn>1063-9667</issn><eissn>2380-6923</eissn><isbn>146734639X</isbn><isbn>9781467346399</isbn><eisbn>9780769548890</eisbn><eisbn>076954889X</eisbn><coden>IEEPAD</coden><abstract>Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the reference voltage level (Vref) in the receiver. The traditional method to choose Vref is to sweep the reference voltage level while performing a link Bit Error Rate (BER) test. This existing method has serious disadvantages like additional circuitry, system overhead and a very long time to completion. In this paper, a fast technique to obtain optimum value of Vref is proposed. It uses a simple density test at the receiver to perform the operation. This technique has been demonstrated in a POD (Pseudo Open-Drain) signaling based single-ended transceiver designed in TSMC 40nm process. System level measurements in the lab at 6 Gb/s data rate prove that this technique is as accurate as the traditional technique in choosing Vref while being several thousand times faster.</abstract><pub>IEEE</pub><doi>10.1109/VLSID.2013.204</doi><tpages>5</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | BER Bit error rate Conferences Density Design engineering Electric potential Integrated circuits memory Optimization Random access memory Receivers Reference voltage Silicon single-ended Timing Transmitters Voltage Vref |
| title | At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T15%3A30%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=At-speed%20I/O%20Test%20for%20Fast%20Vref%20Optimization%20in%20High%20Speed%20Single-ended%20Memory%20Systems&rft.btitle=2013%2026th%20International%20Conference%20on%20VLSI%20Design%20and%202013%2012th%20International%20Conference%20on%20Embedded%20Systems&rft.au=Mukherjee,%20S.&rft.date=2013-01&rft.spage=297&rft.epage=301&rft.pages=297-301&rft.issn=1063-9667&rft.eissn=2380-6923&rft.isbn=146734639X&rft.isbn_list=9781467346399&rft.coden=IEEPAD&rft_id=info:doi/10.1109/VLSID.2013.204&rft_dat=%3Cproquest_6IE%3E1837316677%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9780769548890&rft.eisbn_list=076954889X&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1786217766&rft_id=info:pmid/&rft_ieee_id=6472656&rfr_iscdi=true |