Thermal and power aware task mapping on 3D Network on Chip

High integration and increased elements density in 3D Network on Chip (NoC) will cause more energy consumption and high temperature on chip. By mapping those tasks that have data communication between them to near cores, the communication delay and therefore, power consumption will be reduced. In ad...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	Computers & electrical engineering 2016-04, Vol.51, p.157-167
Hauptverfasser:	Mosayyebzadeh, Amin, Amiraski, Maziar Mehdizadeh, Hessabi, Shaahin
Format:	Artikel
Sprache:	eng
Schlagworte:	3D NoC Chips Delay Fuzzy logic Mapping Networks NoC Reduction System on chip Task mapping Tasks Three dimensional
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!