Memory trade-offs in layered self-corrected min-sum LDPC decoders

This paper proposes two variants which aim at reducing the memory requirements of the self-corrected min-sum (SCMS) with respect to min-sum (MS). The first improvement—SCMS-V1—eliminates the need for check node messages’ signs storage. The second improvement—SCMS-V2—is based on a novel imprecise self-correction rule, which allows the reduction of the erasure bits. We analyze the decoding performance and the hardware cost for the Min-Sum and three variants of the SCMS decoder for two types of regular and irregular LDPC codes, four coding rates, and two message quantizations. The decoding performance analysis indicates that the SCMS-V2 introduces almost no degradation in the error correction capability with respect to the conventional SCMS, while it has an almost 0.5 dB better performance compared to MS. Regarding the implementation analysis, we use an LDPC customizer tool developed by us in order to generate FPGA based LDPC layered architectures with serial AP-LLR processing and multi-codeword decoding support. The synthesis results for Virtex-7 FPGA devices indicate that the SCMS-V2 has similar cost in both BRAM blocks and slices with the Min-Sum decoder and up to 33 % less than SCMS-V1 decoder and up to 40 % less than SCMS decoder.