MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism

Single-thread performance has not improved much over the past few years, despite an ever increasing transistor budget. One of the reasons for this is that there is a speed gap between the processor and main memory, known as the memory wall. A promising method to overcome this memory wall is aggressi...

Ausführliche Beschreibung

Bibliographische Detailangaben

Veröffentlicht in:	IEICE Transactions on Information and Systems 2014, Vol.E97.D(12), pp.3110-3123
Hauptverfasser:	KORA, Yuya, YAMAGUCHI, Kyohei, ANDO, Hideki
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks Dynamical systems Dynamics Expansion instruction-level parallelism memory-level parallelism microprocessor Performance enhancement Processors superscalar processor Walls Windows (intervals)
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!