Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip...

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Veröffentlicht in:Engineering fracture mechanics 2016-03, Vol.153, p.259-277
Hauptverfasser: Raghavan, Sathyanarayanan, Schmadlak, Ilko, Leal, George, Sitaraman, Suresh K.
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Sprache:eng
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