Mixed-mode cohesive zone parameters for sub-micron scale stacked layers to predict microelectronic device reliability

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100nm near the transistors and 1000nm away from the transistors and near the solder bumps. In such BEOL stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data.