FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow

High-level synthesis (HLS) of data-parallel input languages, such as the Compute Unified Device Architecture (CUDA), enables efficient description and implementation of independent computation cores. HLS tools can effectively translate the many threads of computation present in the parallel descript...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2016-06, Vol.24 (6), p.2220-2233
Hauptverfasser:	Yao Chen, Gurumani, Swathi T., Yun Liang, Guofeng Li, Donghui Guo, Rupnow, Kyle, Deming Chen
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture Architecture (computers) Bandwidth Boards Computation CUDA Design analysis Field programmable gate arrays Graphics processing units Hardware high-level synthesis (HLS) Kernel network-on-chip (NoC) parallel languages Parallel processing Performance enhancement Ports (Computers) Very large scale integration
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