Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware

Although custom (and reconfigurable) computing can provide orders-of-magnitude improvements in energy efficiency and performance for many numeric, data-parallel applications, performance on nonnumeric, sequential code is often worse than conventional superscalar processors. This work attempts to imp...

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Veröffentlicht in:	ACM transactions on reconfigurable technology and systems 2016-02, Vol.9 (2), p.1-22
Hauptverfasser:	Zaidi, Ali Mustafa, Greaves, David
Format:	Artikel
Sprache:	eng
Schlagworte:	Chains Compilers Energy management Exposure Flow graphs Hardware Mathematical models Processors
Online-Zugang:	Volltext
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