Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs

This paper presents a circuit-level design and analysis of high-data-rate 3D serial vertical links which exploit the high bandwidth provided by TSV technology. As most of the existing TSVs consume a large amount of die area, the serial configuration can save significant silicon real estate. The performance and jitter characteristic of the proposed 3D link has been accessed for different TSV technologies running worst-case simulations of RC-extracted layouts in 40nm CMOS-technology. Results show that for a 2-layers system with an aggregate bandwidth of 80Gbps, an 8-bit data serialization over 10μm TSVs consumes just 0.15pJ/bit including the clock distribution network.