Sneak-path Testing of Memristor-based Memories

Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale f...

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Hauptverfasser: Kannan, S., Rajendran, J., Karri, R., Sinanoglu, O.
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Rajendran, J.
Karri, R.
Sinanoglu, O.
description Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ~32%.
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fullrecord <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_proquest_miscellaneous_1786218316</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>6472671</ieee_id><sourcerecordid>1786218316</sourcerecordid><originalsourceid>FETCH-LOGICAL-i208t-925b2cd68fcbb0b5d6f8537ab425788e69241eeeedea826edf520713a153373c3</originalsourceid><addsrcrecordid>eNotjjtPwzAUhc1Loi1dWVg6sjhc2_H19YhaHpWKGFoQW-QkDhiSpsTpwL8nqJzl6EifPh3GLgUkQoC9eV2tl4tEglCJFPaITa0hMGh1SmThmI2kIuBopTphY5GiUSkq-3bKRgJQcYtoztk4xk8AIA1mxJL11rsvvnP9x2zjYx-277O2mj35pguxbzueu-jLv912wccLdla5Ovrpf0_Yy_3dZv7IV88Py_ntigcJ1HMrdS6LEqkq8hxyXWJFWhmXp1IbIj88TIUfUnpHEn1ZaQlGKCe0UkYVasKuD95d137vh19ZE2Lh69ptfbuPmTCEUpASOKBXBzQMvmzXhcZ1PxmmRuJg_AX1ClQ2</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>1786218316</pqid></control><display><type>conference_proceeding</type><title>Sneak-path Testing of Memristor-based Memories</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Kannan, S. ; Rajendran, J. ; Karri, R. ; Sinanoglu, O.</creator><creatorcontrib>Kannan, S. ; Rajendran, J. ; Karri, R. ; Sinanoglu, O.</creatorcontrib><description>Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ~32%.</description><identifier>ISSN: 1063-9667</identifier><identifier>ISBN: 146734639X</identifier><identifier>ISBN: 9781467346399</identifier><identifier>EISSN: 2380-6923</identifier><identifier>EISBN: 9780769548890</identifier><identifier>EISBN: 076954889X</identifier><identifier>DOI: 10.1109/VLSID.2013.219</identifier><identifier>CODEN: IEEPAD</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit faults ; Conferences ; Current measurement ; Defects ; Density ; Design engineering ; emerging memory technologies ; fault modeling ; Integrated circuit modeling ; Integrated circuits ; Memory devices ; memory testing ; Memristors ; metal-oxide memristors ; Nanoscale devices ; Resistance ; Resistors ; Testing ; Very large scale integration</subject><ispartof>2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013, p.386-391</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6472671$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,776,780,785,786,2052,27901,27902,54895</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6472671$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Kannan, S.</creatorcontrib><creatorcontrib>Rajendran, J.</creatorcontrib><creatorcontrib>Karri, R.</creatorcontrib><creatorcontrib>Sinanoglu, O.</creatorcontrib><title>Sneak-path Testing of Memristor-based Memories</title><title>2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems</title><addtitle>ICVD</addtitle><description>Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ~32%.</description><subject>Circuit faults</subject><subject>Conferences</subject><subject>Current measurement</subject><subject>Defects</subject><subject>Density</subject><subject>Design engineering</subject><subject>emerging memory technologies</subject><subject>fault modeling</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuits</subject><subject>Memory devices</subject><subject>memory testing</subject><subject>Memristors</subject><subject>metal-oxide memristors</subject><subject>Nanoscale devices</subject><subject>Resistance</subject><subject>Resistors</subject><subject>Testing</subject><subject>Very large scale integration</subject><issn>1063-9667</issn><issn>2380-6923</issn><isbn>146734639X</isbn><isbn>9781467346399</isbn><isbn>9780769548890</isbn><isbn>076954889X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2013</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotjjtPwzAUhc1Loi1dWVg6sjhc2_H19YhaHpWKGFoQW-QkDhiSpsTpwL8nqJzl6EifPh3GLgUkQoC9eV2tl4tEglCJFPaITa0hMGh1SmThmI2kIuBopTphY5GiUSkq-3bKRgJQcYtoztk4xk8AIA1mxJL11rsvvnP9x2zjYx-277O2mj35pguxbzueu-jLv912wccLdla5Ovrpf0_Yy_3dZv7IV88Py_ntigcJ1HMrdS6LEqkq8hxyXWJFWhmXp1IbIj88TIUfUnpHEn1ZaQlGKCe0UkYVasKuD95d137vh19ZE2Lh69ptfbuPmTCEUpASOKBXBzQMvmzXhcZ1PxmmRuJg_AX1ClQ2</recordid><startdate>201301</startdate><enddate>201301</enddate><creator>Kannan, S.</creator><creator>Rajendran, J.</creator><creator>Karri, R.</creator><creator>Sinanoglu, O.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>201301</creationdate><title>Sneak-path Testing of Memristor-based Memories</title><author>Kannan, S. ; Rajendran, J. ; Karri, R. ; Sinanoglu, O.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i208t-925b2cd68fcbb0b5d6f8537ab425788e69241eeeedea826edf520713a153373c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2013</creationdate><topic>Circuit faults</topic><topic>Conferences</topic><topic>Current measurement</topic><topic>Defects</topic><topic>Density</topic><topic>Design engineering</topic><topic>emerging memory technologies</topic><topic>fault modeling</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuits</topic><topic>Memory devices</topic><topic>memory testing</topic><topic>Memristors</topic><topic>metal-oxide memristors</topic><topic>Nanoscale devices</topic><topic>Resistance</topic><topic>Resistors</topic><topic>Testing</topic><topic>Very large scale integration</topic><toplevel>online_resources</toplevel><creatorcontrib>Kannan, S.</creatorcontrib><creatorcontrib>Rajendran, J.</creatorcontrib><creatorcontrib>Karri, R.</creatorcontrib><creatorcontrib>Sinanoglu, O.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kannan, S.</au><au>Rajendran, J.</au><au>Karri, R.</au><au>Sinanoglu, O.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Sneak-path Testing of Memristor-based Memories</atitle><btitle>2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems</btitle><stitle>ICVD</stitle><date>2013-01</date><risdate>2013</risdate><spage>386</spage><epage>391</epage><pages>386-391</pages><issn>1063-9667</issn><eissn>2380-6923</eissn><isbn>146734639X</isbn><isbn>9781467346399</isbn><eisbn>9780769548890</eisbn><eisbn>076954889X</eisbn><coden>IEEPAD</coden><abstract>Memristors are an attractive option for use in future memory architectures due to their non-volatility, low power operation and compactness. Notwithstanding these advantages, memristors and memristor-based memories are prone to high defect densities due to the non-deterministic nature of nanoscale fabrication. As a first step, we will examine the defect mechanisms in memristors and develop efficient fault models. Next, the memory subsystem has to be tested. The typical approach to testing a memory subsystem entails testing one memory element at a time. This is time consuming and does not scale for dense, memristor-based memories. We propose an efficient testing technique to test memristor-based memories. The proposed scheme uses sneak-paths inherent in crossbar memories to test multiple memristors at the same time and thereby reduces the test time by ~32%.</abstract><pub>IEEE</pub><doi>10.1109/VLSID.2013.219</doi><tpages>6</tpages></addata></record>
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identifier ISSN: 1063-9667
ispartof 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems, 2013, p.386-391
issn 1063-9667
2380-6923
language eng
recordid cdi_proquest_miscellaneous_1786218316
source IEEE Electronic Library (IEL) Conference Proceedings
subjects Circuit faults
Conferences
Current measurement
Defects
Density
Design engineering
emerging memory technologies
fault modeling
Integrated circuit modeling
Integrated circuits
Memory devices
memory testing
Memristors
metal-oxide memristors
Nanoscale devices
Resistance
Resistors
Testing
Very large scale integration
title Sneak-path Testing of Memristor-based Memories
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T22%3A05%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Sneak-path%20Testing%20of%20Memristor-based%20Memories&rft.btitle=2013%2026th%20International%20Conference%20on%20VLSI%20Design%20and%202013%2012th%20International%20Conference%20on%20Embedded%20Systems&rft.au=Kannan,%20S.&rft.date=2013-01&rft.spage=386&rft.epage=391&rft.pages=386-391&rft.issn=1063-9667&rft.eissn=2380-6923&rft.isbn=146734639X&rft.isbn_list=9781467346399&rft.coden=IEEPAD&rft_id=info:doi/10.1109/VLSID.2013.219&rft_dat=%3Cproquest_6IE%3E1786218316%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9780769548890&rft.eisbn_list=076954889X&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1786218316&rft_id=info:pmid/&rft_ieee_id=6472671&rfr_iscdi=true