On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches

When hardware cache coherence scales to many cores on chip, over saturated traffic of the shared memory system may offset the benefit from massive hardware concurrency. In this article, we investigate the cost of a write-update protocol in terms of on-chip memory network traffic and its adverse effe...

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Veröffentlicht in:	ACM transactions on embedded computing systems 2014-03, Vol.13 (3s), p.1-21
Hauptverfasser:	Yang, Qiang, Fu, Jian, Poss, Raphael, Jesshope, Chris
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture Coherence Concurrency Hardware Mathematical models Networks Traffic engineering Traffic flow
Online-Zugang:	Volltext
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