A dual redundancy radiation-hardened flip-flop based on a C-element in a 65 nm process
A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different...
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| Veröffentlicht in: | Journal of semiconductors 2013-09, Vol.34 (9), p.160-163 |
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| container_title | Journal of semiconductors |
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| creator | 陈刚 高博 龚敏 |
| description | A radiation-hardened flip-flop is proposed to mitigate the single event upset （SEU） effect. Immunity was achieved through the use of C-elements and redundant storage elements. It takes advantage of the property of a C-element in which it enters a high impedance mode when its inputs are of different logic values. Redundant storage nodes are then used to drive the C-elements so that a single upset pulse in any storage will be prevented from altering the state of the output of the flip-flop. The flip-flop was implemented using 48 transistors and occupied an area of 30.78 μm2, using 65 nm CMOS process. It consumed 22.6% fewer transistors as compared to the traditional SEU resilient TMR flip-flop. |
| doi_str_mv | 10.1088/1674-4926/34/9/095012 |
| format | Article |
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| fulltext | fulltext |
| identifier | ISSN: 1674-4926 |
| ispartof | Journal of semiconductors, 2013-09, Vol.34 (9), p.160-163 |
| issn | 1674-4926 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_1730103925 |
| source | Institute of Physics Journals; Alma/SFX Local Collection |
| subjects | CMOS CMOS工艺 Flip-flops High impedance Redundant Semiconductor devices Semiconductors Single event upsets Transistors 元件 冗余存储 制程 双冗余 抗辐射 触发器 辐射加固 |
| title | A dual redundancy radiation-hardened flip-flop based on a C-element in a 65 nm process |
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