Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators

We present a low-jitter design for a 10-bit second-order frequency shift oscillator time-to-digital converter (FSOTDC). As described herein, we analyze the relation between performance and FSOTDC parameters and provide insight to support the design of the FSOTDC. Results show that an oscillator jitt...

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Veröffentlicht in:	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Communications and Computer Sciences, 2015/07/01, Vol.E98.A(7), pp.1475-1481
Hauptverfasser:	OKUNO, Keisuke, KONISHI, Toshihiro, IZUMI, Shintaro, YOSHIMOTO, Masahiko, KAWAGUCHI, Hiroshi
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks CMOS Converters design methodology Frequency shift FSO Jitter Oscillators Sampling TDC
Online-Zugang:	Volltext
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