Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity

Redundant Binary Signed Digit Adder and Multiplier circuits are logic circuits which are designed to perform high-speed arithmetic operations. Fast RBSD adder cell, proposed by Kal and Rajshekhar in 1990 was modified by Neelam Sharma in 2006 using universal logic. The proposed adder is re-modified f...

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Veröffentlicht in:	International Journal of Engineering and Technology 2011-06, Vol.3 (3), p.274-278
Hauptverfasser:	Saxena, Rakesh Kumar, Sharma, Neelam, Wadhwani, A K
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuits Complexity Digits Gates (circuits) High speed Multipliers Redundant VHDL
Online-Zugang:	Volltext
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