On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs
In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is...
Gespeichert in:
Veröffentlicht in: | Integration (Amsterdam) 2014, Vol.47 (4), p.387-407 |
---|---|
Hauptverfasser: | , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 407 |
---|---|
container_issue | 4 |
container_start_page | 387 |
container_title | Integration (Amsterdam) |
container_volume | 47 |
creator | Michail, H.E. Athanasiou, G.S. Theodoridis, G. Goutis, C.E. |
description | In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.
•High-throughput and area-efficient SHA-256/512 and SHA-1/256/512 multi-mode architectures.•Systematic design flow for developing multi-hash-mode architectures.•Comparisons with multi-mode architectures produced by commercial synthesis tools.•Comparisons of the proposed architectures with similar ones found in the literature. |
doi_str_mv | 10.1016/j.vlsi.2014.02.004 |
format | Article |
fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1677979840</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0167926014000145</els_id><sourcerecordid>1677979840</sourcerecordid><originalsourceid>FETCH-LOGICAL-c466t-7d0a3b996edae66f1cc47bbf5c999bb5296197ddde3ea3a0ff8526a9c7c4a5b73</originalsourceid><addsrcrecordid>eNqNkctq3TAURUVpobdpfqAjTQqd2JFlS7KgkxCaBwTSQTMWsnRk6-JXJflC_j4yN3RYMjqTtfeBvRD6VpGyIhW_OpanMfqSkqopCS0JaT6gQ9UKWghG6Ud0yJAoJOXkM_oS45GQTAp2QP3TjNMA2MIJxmWdYE54cXjw_VCkISxbP6xbwnq2WAfQBTjnjd-paRuTL6bFAjbhZU1LH_Q6eIMHHYfcF30_R-xnfPv77jp-RZ-cHiNcvt0L9Hz768_NffH4dPdwc_1YmIbzVAhLdN1JycFq4NxVxjSi6xwzUsquY1TySgprLdSga02caxnlWhphGs06UV-gH-feNSx_N4hJTT4aGEc9w7JFlWcQUsi2Ie9AKSE1Ey3PKD2jJiwxBnBqDX7S4UVVRO0C1FHtAtQuQBGqsoAc-v7Wr6PRowt6Nj7-S9KWCdaKNnM_zxzkXU4egor7wgasD2CSsov_35tXHkWdcg</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1620035786</pqid></control><display><type>article</type><title>On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs</title><source>ScienceDirect Journals (5 years ago - present)</source><creator>Michail, H.E. ; Athanasiou, G.S. ; Theodoridis, G. ; Goutis, C.E.</creator><creatorcontrib>Michail, H.E. ; Athanasiou, G.S. ; Theodoridis, G. ; Goutis, C.E.</creatorcontrib><description>In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.
•High-throughput and area-efficient SHA-256/512 and SHA-1/256/512 multi-mode architectures.•Systematic design flow for developing multi-hash-mode architectures.•Comparisons with multi-mode architectures produced by commercial synthesis tools.•Comparisons of the proposed architectures with similar ones found in the literature.</description><identifier>ISSN: 0167-9260</identifier><identifier>EISSN: 1872-7522</identifier><identifier>DOI: 10.1016/j.vlsi.2014.02.004</identifier><identifier>CODEN: IVJODL</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Applied sciences ; Architecture ; Authentication ; Circuit properties ; Cryptography ; Design engineering ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Field programmable gate arrays ; FPGA ; Hash ; Hash based algorithms ; Integrated circuits ; Multi-mode ; Synthesis</subject><ispartof>Integration (Amsterdam), 2014, Vol.47 (4), p.387-407</ispartof><rights>2014 Elsevier B.V.</rights><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c466t-7d0a3b996edae66f1cc47bbf5c999bb5296197ddde3ea3a0ff8526a9c7c4a5b73</citedby><cites>FETCH-LOGICAL-c466t-7d0a3b996edae66f1cc47bbf5c999bb5296197ddde3ea3a0ff8526a9c7c4a5b73</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://dx.doi.org/10.1016/j.vlsi.2014.02.004$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,780,784,3548,4022,27922,27923,27924,45994</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=28575878$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Michail, H.E.</creatorcontrib><creatorcontrib>Athanasiou, G.S.</creatorcontrib><creatorcontrib>Theodoridis, G.</creatorcontrib><creatorcontrib>Goutis, C.E.</creatorcontrib><title>On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs</title><title>Integration (Amsterdam)</title><description>In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.
•High-throughput and area-efficient SHA-256/512 and SHA-1/256/512 multi-mode architectures.•Systematic design flow for developing multi-hash-mode architectures.•Comparisons with multi-mode architectures produced by commercial synthesis tools.•Comparisons of the proposed architectures with similar ones found in the literature.</description><subject>Applied sciences</subject><subject>Architecture</subject><subject>Authentication</subject><subject>Circuit properties</subject><subject>Cryptography</subject><subject>Design engineering</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Field programmable gate arrays</subject><subject>FPGA</subject><subject>Hash</subject><subject>Hash based algorithms</subject><subject>Integrated circuits</subject><subject>Multi-mode</subject><subject>Synthesis</subject><issn>0167-9260</issn><issn>1872-7522</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><recordid>eNqNkctq3TAURUVpobdpfqAjTQqd2JFlS7KgkxCaBwTSQTMWsnRk6-JXJflC_j4yN3RYMjqTtfeBvRD6VpGyIhW_OpanMfqSkqopCS0JaT6gQ9UKWghG6Ud0yJAoJOXkM_oS45GQTAp2QP3TjNMA2MIJxmWdYE54cXjw_VCkISxbP6xbwnq2WAfQBTjnjd-paRuTL6bFAjbhZU1LH_Q6eIMHHYfcF30_R-xnfPv77jp-RZ-cHiNcvt0L9Hz768_NffH4dPdwc_1YmIbzVAhLdN1JycFq4NxVxjSi6xwzUsquY1TySgprLdSga02caxnlWhphGs06UV-gH-feNSx_N4hJTT4aGEc9w7JFlWcQUsi2Ie9AKSE1Ey3PKD2jJiwxBnBqDX7S4UVVRO0C1FHtAtQuQBGqsoAc-v7Wr6PRowt6Nj7-S9KWCdaKNnM_zxzkXU4egor7wgasD2CSsov_35tXHkWdcg</recordid><startdate>2014</startdate><enddate>2014</enddate><creator>Michail, H.E.</creator><creator>Athanasiou, G.S.</creator><creator>Theodoridis, G.</creator><creator>Goutis, C.E.</creator><general>Elsevier B.V</general><general>Elsevier</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>2014</creationdate><title>On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs</title><author>Michail, H.E. ; Athanasiou, G.S. ; Theodoridis, G. ; Goutis, C.E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c466t-7d0a3b996edae66f1cc47bbf5c999bb5296197ddde3ea3a0ff8526a9c7c4a5b73</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Applied sciences</topic><topic>Architecture</topic><topic>Authentication</topic><topic>Circuit properties</topic><topic>Cryptography</topic><topic>Design engineering</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Field programmable gate arrays</topic><topic>FPGA</topic><topic>Hash</topic><topic>Hash based algorithms</topic><topic>Integrated circuits</topic><topic>Multi-mode</topic><topic>Synthesis</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Michail, H.E.</creatorcontrib><creatorcontrib>Athanasiou, G.S.</creatorcontrib><creatorcontrib>Theodoridis, G.</creatorcontrib><creatorcontrib>Goutis, C.E.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Integration (Amsterdam)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Michail, H.E.</au><au>Athanasiou, G.S.</au><au>Theodoridis, G.</au><au>Goutis, C.E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs</atitle><jtitle>Integration (Amsterdam)</jtitle><date>2014</date><risdate>2014</risdate><volume>47</volume><issue>4</issue><spage>387</spage><epage>407</epage><pages>387-407</pages><issn>0167-9260</issn><eissn>1872-7522</eissn><coden>IVJODL</coden><abstract>In this paper, area-efficient and high-throughput multi-mode architectures for the SHA-1 and SHA-2 hash families are proposed and implemented in several FPGA technologies. Additionally a systematic flow for designing multi-mode architectures (implementing more than one function) of these families is introduced. Compared to the corresponding architectures that are produced by a commercial synthesis tool, the proposed ones are better in terms of both area (at least 40%) and throughput/area (from 32% up to 175%). Finally, the proposed architectures outperform similar existing ones in terms of throughput and throughput/area, from 4.2× up to 279.4× and from 1.2× up to 5.5×, respectively.
•High-throughput and area-efficient SHA-256/512 and SHA-1/256/512 multi-mode architectures.•Systematic design flow for developing multi-hash-mode architectures.•Comparisons with multi-mode architectures produced by commercial synthesis tools.•Comparisons of the proposed architectures with similar ones found in the literature.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/j.vlsi.2014.02.004</doi><tpages>21</tpages></addata></record> |
fulltext | fulltext |
identifier | ISSN: 0167-9260 |
ispartof | Integration (Amsterdam), 2014, Vol.47 (4), p.387-407 |
issn | 0167-9260 1872-7522 |
language | eng |
recordid | cdi_proquest_miscellaneous_1677979840 |
source | ScienceDirect Journals (5 years ago - present) |
subjects | Applied sciences Architecture Authentication Circuit properties Cryptography Design engineering Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Field programmable gate arrays FPGA Hash Hash based algorithms Integrated circuits Multi-mode Synthesis |
title | On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T16%3A39%3A16IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=On%20the%20development%20of%20high-throughput%20and%20area-efficient%20multi-mode%20cryptographic%20hash%20designs%20in%20FPGAs&rft.jtitle=Integration%20(Amsterdam)&rft.au=Michail,%20H.E.&rft.date=2014&rft.volume=47&rft.issue=4&rft.spage=387&rft.epage=407&rft.pages=387-407&rft.issn=0167-9260&rft.eissn=1872-7522&rft.coden=IVJODL&rft_id=info:doi/10.1016/j.vlsi.2014.02.004&rft_dat=%3Cproquest_cross%3E1677979840%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1620035786&rft_id=info:pmid/&rft_els_id=S0167926014000145&rfr_iscdi=true |