One electron-based smallest flexible logic cell
A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exh...
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| Veröffentlicht in: | Applied physics letters 2012-10, Vol.101 (18) |
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| container_title | Applied physics letters |
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| creator | Kim, S. J. Lee, J. J. Kang, H. J. Choi, J. B. Yu, Y.-S. Takahashi, Y. Hasko, D. G. |
| description | A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power. |
| doi_str_mv | 10.1063/1.4761935 |
| format | Article |
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This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.</description><identifier>ISSN: 0003-6951</identifier><identifier>EISSN: 1077-3118</identifier><identifier>DOI: 10.1063/1.4761935</identifier><language>eng</language><subject>Arithmetic ; Blocking ; Electric potential ; Gates ; Logic ; Nanostructure ; Single-electron transistors ; Voltage</subject><ispartof>Applied physics letters, 2012-10, Vol.101 (18)</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c328t-d01117fb14763d27c5bfa362e8ce02bf8fbf4bf00325344272931b834496be403</citedby><cites>FETCH-LOGICAL-c328t-d01117fb14763d27c5bfa362e8ce02bf8fbf4bf00325344272931b834496be403</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Kim, S. 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Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.</description><subject>Arithmetic</subject><subject>Blocking</subject><subject>Electric potential</subject><subject>Gates</subject><subject>Logic</subject><subject>Nanostructure</subject><subject>Single-electron transistors</subject><subject>Voltage</subject><issn>0003-6951</issn><issn>1077-3118</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><recordid>eNotkE1Lw0AYhBdRMFYP_oMc9ZB2332zHzlK8QsKveh5yW7elcgmqbst6L83pT3NDAzDwzB2D3wJXOEKlrVW0KC8YAVwrSsEMJes4JxjpRoJ1-wm5-85SoFYsNV2pJIi-X2axsq1mboyD22MlPdliPTbu0hlnL56X3qK8ZZdhTZmujvrgn2-PH-s36rN9vV9_bSpPAqzrzoOADo4mGmwE9pLF1pUgownLlwwwYXahRlKSKxroUWD4MxsG-Wo5rhgD6fdXZp-DjOMHfp8BGhHmg7ZgtIguTS6mauPp6pPU86Jgt2lfmjTnwVuj6dYsOdT8B_KqFGU</recordid><startdate>20121029</startdate><enddate>20121029</enddate><creator>Kim, S. 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G.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c328t-d01117fb14763d27c5bfa362e8ce02bf8fbf4bf00325344272931b834496be403</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Arithmetic</topic><topic>Blocking</topic><topic>Electric potential</topic><topic>Gates</topic><topic>Logic</topic><topic>Nanostructure</topic><topic>Single-electron transistors</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Kim, S. J.</creatorcontrib><creatorcontrib>Lee, J. J.</creatorcontrib><creatorcontrib>Kang, H. J.</creatorcontrib><creatorcontrib>Choi, J. B.</creatorcontrib><creatorcontrib>Yu, Y.-S.</creatorcontrib><creatorcontrib>Takahashi, Y.</creatorcontrib><creatorcontrib>Hasko, D. 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G.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>One electron-based smallest flexible logic cell</atitle><jtitle>Applied physics letters</jtitle><date>2012-10-29</date><risdate>2012</risdate><volume>101</volume><issue>18</issue><issn>0003-6951</issn><eissn>1077-3118</eissn><abstract>A one electron-based operating half-adder, the smallest arithmetic block, has been implemented on silicon-on-insulator structure whose basic element is a nanoscale single-electron transistor (SET) with two symmetrical side-wall gates. Grayscale contour plots of the resulting cell output voltages exhibit the Coulomb blockade-induced periodic alternating high/low features. Their voltage transfer characteristics display typical Sum and Carry-Out functions for binary, multi-valued (MV), and binary-MV mixed input voltages. Moreover, the half-adder function converts into a subtraction mode by adjusting control gates of the SET element. This flexible multi-valued cell provides an arithmetic block for the SET MV logic family of high density integration, operating with ultra-low power.</abstract><doi>10.1063/1.4761935</doi></addata></record> |
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| ispartof | Applied physics letters, 2012-10, Vol.101 (18) |
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| language | eng |
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| source | AIP Digital Archive; Alma/SFX Local Collection; AIP Journals (American Institute of Physics) |
| subjects | Arithmetic Blocking Electric potential Gates Logic Nanostructure Single-electron transistors Voltage |
| title | One electron-based smallest flexible logic cell |
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