Impact of parasitics on even symmetric split-capacitor arrays

ABSTRACT This paper analyzes the impact of parasitic capacitances in the performance of split capacitive‐based digital‐to‐analog converter arrays and presents a procedure for the optimal sizing of these structures for given linearity specifications. It also demonstrates that parasitics are often the...

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Veröffentlicht in:	International journal of circuit theory and applications 2013-09, Vol.41 (9), p.972-987
Hauptverfasser:	Rodríguez-Pérez, Alberto, Delgado-Restituto, Manuel, Medeiro, Fernando
Format:	Artikel
Sprache:	eng
Schlagworte:	Arrays Capacitors Converters DAC Dummies Expenses Linearity low power low voltage mismatch parasitic capacitances Prototypes Sizing successive-approximation ADC
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