Shared Architecture for Encryption/Decryption of AES
Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. The AES algorithm is capable of using cryptographic keys of 128, 192, and...
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| Veröffentlicht in: | International journal of computer applications 2013-01, Vol.69 (18), p.1-6 |
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| container_title | International journal of computer applications |
| container_volume | 69 |
| creator | Sharma, Richa Kumari Biradar, S R Singh, B P |
| description | Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. The AES algorithm is capable of using cryptographic keys of 128, 192, and 256 bits to encrypt and decrypt data in blocks of 128 bits. This standard is based on the Rijndael algorithm. Here this paper presents the shared architectures for both encryption and decryption. Shared architecture reduces the area as well as the path delay. This methodology uses VHDL implementation of all the modules and results are concluded in terms of Delay and Frequency. |
| doi_str_mv | 10.5120/12068-8067 |
| format | Article |
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| ispartof | International journal of computer applications, 2013-01, Vol.69 (18), p.1-6 |
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| source | Elektronische Zeitschriftenbibliothek - Frei zugängliche E-Journals |
| subjects | Algorithms Architecture Cryptography Delay Electronics Encryption Mathematical analysis VHDL |
| title | Shared Architecture for Encryption/Decryption of AES |
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