A 1.5-GHz 130-nm Itanium super( registered ) 2 Processor with 6-MB on-die L3 cache

This 130-nm Itanium 2 processor implements the explicitly parallel instruction computing (EPIC) architecture and features an on-die 6-MB 24-way set-associative level-3 cache. The 374-mm super(2) die contains 410 M transistors and is implemented in a dual-V sub(t) process with six Cu interconnect lay...

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Veröffentlicht in:IEEE journal of solid-state circuits 2003-01, Vol.38 (11)
Hauptverfasser: Rusu, S, Stinson, J, Tam, S, Leung, J, Muljono, H, Cherkauer, B
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container_issue 11
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container_title IEEE journal of solid-state circuits
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creator Rusu, S
Stinson, J
Tam, S
Leung, J
Muljono, H
Cherkauer, B
description This 130-nm Itanium 2 processor implements the explicitly parallel instruction computing (EPIC) architecture and features an on-die 6-MB 24-way set-associative level-3 cache. The 374-mm super(2) die contains 410 M transistors and is implemented in a dual-V sub(t) process with six Cu interconnect layers and FSG dielectric. The processor runs at 1.5 GHz at 1.3 V and dissipates a maximum of 130 W. This paper reviews circuit design and package details, power delivery, the reliability, availability, and serviceability (RAS) features, design for test (DFT), and design for manufacturability (DFM) features, as well as an overview of the design and verification methodology. The fuse-based clock deskew circuit achieves 24-ps skew across the entire die, while the scan-based skew control further reduces it to 7 ps. The 128-bit front-side bus has a bandwidth of 6.4 GB/s and supports up to four processors on a single bus.
doi_str_mv 10.1109/JSSC.2003.818293
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subjects Availability
Buses (vehicles)
Circuit design
Circuits
Clocks
Design for manufacturability
Microprocessors
Packages
title A 1.5-GHz 130-nm Itanium super( registered ) 2 Processor with 6-MB on-die L3 cache
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