Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture

Since the power consumption of FPGA is larger than that of ASIC under the condition to perform the same function using the same scaling, the application of FPGA is limited especially in portable electronic devices. In this paper, we propose a novel low-power FPGA architecture based on coarse-grained...

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Veröffentlicht in:	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Communications and Computer Sciences, 2011/12/01, Vol.E94.A(12), pp.2519-2527
Hauptverfasser:	LI, Ce, DONG, Yiping, WATANABE, Takahiro
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithms Architecture Field programmable gate arrays FPGA Gating and risering low power Mathematical analysis Placement Portability Power consumption power domain
Online-Zugang:	Volltext
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