Cycling Effect on the Random Telegraph Noise Instabilities of nor and nand Flash Arrays
The impact of program/erase (P/E) cycling on the random telegraph noise (RTN) threshold voltage instability of NOR and NAND flash memories is studied in detail. RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations o...
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| Veröffentlicht in: | IEEE electron device letters 2008-08, Vol.29 (8), p.941-943 |
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| creator | Compagnoni, C.M. Spinelli, A.S. Beltrami, S. Bonanomi, M. Visconti, A. |
| description | The impact of program/erase (P/E) cycling on the random telegraph noise (RTN) threshold voltage instability of NOR and NAND flash memories is studied in detail. RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies. |
| doi_str_mv | 10.1109/LED.2008.2000964 |
| format | Article |
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RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies.</description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/LED.2008.2000964</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Arrays ; Circuit properties ; Cycles ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Doping ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; Failure analysis ; Flash memories ; Flash memory ; Flash memory (computers) ; Fluctuations ; Instability ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Multilevel ; Noise ; Nonvolatile memory ; Probability distribution ; random telegraph noise (RTN) ; Semiconductor electronics. Microelectronics. Optoelectronics. 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RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies.</description><subject>Applied sciences</subject><subject>Arrays</subject><subject>Circuit properties</subject><subject>Cycles</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Doping</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Failure analysis</subject><subject>Flash memories</subject><subject>Flash memory</subject><subject>Flash memory (computers)</subject><subject>Fluctuations</subject><subject>Instability</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Multilevel</subject><subject>Noise</subject><subject>Nonvolatile memory</subject><subject>Probability distribution</subject><subject>random telegraph noise (RTN)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Stability</subject><subject>Statistical analysis</subject><subject>Stress</subject><subject>Tail</subject><subject>Telegraphy</subject><subject>Testing, measurement, noise and reliability</subject><subject>Threshold voltage</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkc1rGzEQxUVJoU6aeyEXEQj0solGHyvrGFynDZgUSkKPQpZHscJacqT1wf99ZWxy6OXNYX7zmHlDyDdgtwDM3C3mP245Y9ODMNPLT2QCSk07pnpxRiZMS-gEsP4LOa_1jTGQUssJ-Tvb-yGmVzoPAf1Ic6LjGukfl1Z5Q59xwNfitmv6lGNF-pjq6JZxiGPESnOgKRfaUJoO8jC4uqb3pbh9_Uo-BzdUvDzVC_LyMH-e_eoWv38-zu4XnZdgxo475EGh0s4JbqZCer7UwnsujdYGpeJaMcd8j9yEsIKwVEunVkqiZwbaaRfk-9F3W_L7DutoN7F6HAaXMO-qhV6DUCA4b-j1f-hb3pXUtrMGONda9tAgdoR8ybUWDHZb4saVvQVmD0HbFrQ9BG1PQbeRm5Ovq94NobjkY_2Y40wJmArRuKsjFxHxoy2VhvYo8Q90V4Ru</recordid><startdate>20080801</startdate><enddate>20080801</enddate><creator>Compagnoni, C.M.</creator><creator>Spinelli, A.S.</creator><creator>Beltrami, S.</creator><creator>Bonanomi, M.</creator><creator>Visconti, A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Solid state devices</topic><topic>Stability</topic><topic>Statistical analysis</topic><topic>Stress</topic><topic>Tail</topic><topic>Telegraphy</topic><topic>Testing, measurement, noise and reliability</topic><topic>Threshold voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Compagnoni, C.M.</creatorcontrib><creatorcontrib>Spinelli, A.S.</creatorcontrib><creatorcontrib>Beltrami, S.</creatorcontrib><creatorcontrib>Bonanomi, M.</creatorcontrib><creatorcontrib>Visconti, A.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Compagnoni, C.M.</au><au>Spinelli, A.S.</au><au>Beltrami, S.</au><au>Bonanomi, M.</au><au>Visconti, A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Cycling Effect on the Random Telegraph Noise Instabilities of nor and nand Flash Arrays</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>2008-08-01</date><risdate>2008</risdate><volume>29</volume><issue>8</issue><spage>941</spage><epage>943</epage><pages>941-943</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>The impact of program/erase (P/E) cycling on the random telegraph noise (RTN) threshold voltage instability of NOR and NAND flash memories is studied in detail. RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/LED.2008.2000964</doi><tpages>3</tpages></addata></record> |
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| subjects | Applied sciences Arrays Circuit properties Cycles Design. Technologies. Operation analysis. Testing Digital circuits Doping Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Failure analysis Flash memories Flash memory Flash memory (computers) Fluctuations Instability Integrated circuits Integrated circuits by function (including memories and processors) Multilevel Noise Nonvolatile memory Probability distribution random telegraph noise (RTN) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Stability Statistical analysis Stress Tail Telegraphy Testing, measurement, noise and reliability Threshold voltage |
| title | Cycling Effect on the Random Telegraph Noise Instabilities of nor and nand Flash Arrays |
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