Reducing burn-in time through high-voltage stress test and Weibull statistical analysis
To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for re...
Gespeichert in:
| Veröffentlicht in: | IEEE design & test of computers 2006-03, Vol.23 (2), p.88-98 |
|---|---|
| Hauptverfasser: | , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 98 |
|---|---|
| container_issue | 2 |
| container_start_page | 88 |
| container_title | IEEE design & test of computers |
| container_volume | 23 |
| creator | Zakaria, M.F. Kassim, Z.A. Ooi, M.P.-L. Demidenko, S. |
| description | To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the device's failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in. |
| doi_str_mv | 10.1109/MDT.2006.50 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_1671341080</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1613787</ieee_id><sourcerecordid>1671341080</sourcerecordid><originalsourceid>FETCH-LOGICAL-c344t-4a9ffdba5263f2e1b11f35f7364e65583f5fc74f6b9ac6d007537c1baecba88f3</originalsourceid><addsrcrecordid>eNp90U1LAzEQBuAgCtbqyaOXxYMIsjWz-dyj1E-oCFLpMWTTpE3Z7tZNVui_N6WC4MHTwPAwzMyL0DngEQAub1_vp6MCYz5i-AANgDGZQwnyEA2woDgXVLBjdBLCCmMMwPkAzd7tvDe-WWRV3zW5b7Lo1zaLy67tF8ts6RfL_Kuto17YLMTOhpBFG2Kmm3k2s77q6zr1dfQheqPr1Nf1Nvhwio6croM9-6lD9PH4MB0_55O3p5fx3SQ3hNKYU106N680KzhxhYUKwBHmBOHU8rQ-ccwZQR2vSm34HGPBiDBQaWsqLaUjQ3S1n7vp2s8-babWPhhb17qxbR9UISUFwkSC1_9C4AIIBSxxopd_6KpNz0lnqBIKKDCXZUI3e2S6NoTOOrXp_Fp3WwVY7cJQKQy1C0Ox3ciLvfbW2l_JgQgpyDcHTIWM</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>912120689</pqid></control><display><type>article</type><title>Reducing burn-in time through high-voltage stress test and Weibull statistical analysis</title><source>IEEE Electronic Library (IEL)</source><creator>Zakaria, M.F. ; Kassim, Z.A. ; Ooi, M.P.-L. ; Demidenko, S.</creator><creatorcontrib>Zakaria, M.F. ; Kassim, Z.A. ; Ooi, M.P.-L. ; Demidenko, S.</creatorcontrib><description>To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the device's failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in.</description><identifier>ISSN: 0740-7475</identifier><identifier>ISSN: 2168-2356</identifier><identifier>EISSN: 1558-1918</identifier><identifier>EISSN: 2168-2364</identifier><identifier>DOI: 10.1109/MDT.2006.50</identifier><identifier>CODEN: IDTCEC</identifier><language>eng</language><publisher>Los Alamitos: IEEE Computer Society</publisher><subject>Burn-in ; burn-in reduction ; Circuit testing ; Circuits ; CMOS technology ; Computer simulation ; Costs ; Design engineering ; Devices ; Industry standards ; integral circuit testing ; Integrated circuit testing ; Life estimation ; Semiconductor device manufacture ; Statistical analysis ; Stress ; Stresses ; Temperature ; voltage stress ; Wafer scale integration ; Weibull analysis</subject><ispartof>IEEE design & test of computers, 2006-03, Vol.23 (2), p.88-98</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2006</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c344t-4a9ffdba5263f2e1b11f35f7364e65583f5fc74f6b9ac6d007537c1baecba88f3</citedby><cites>FETCH-LOGICAL-c344t-4a9ffdba5263f2e1b11f35f7364e65583f5fc74f6b9ac6d007537c1baecba88f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1613787$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1613787$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Zakaria, M.F.</creatorcontrib><creatorcontrib>Kassim, Z.A.</creatorcontrib><creatorcontrib>Ooi, M.P.-L.</creatorcontrib><creatorcontrib>Demidenko, S.</creatorcontrib><title>Reducing burn-in time through high-voltage stress test and Weibull statistical analysis</title><title>IEEE design & test of computers</title><addtitle>MDT</addtitle><description>To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the device's failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in.</description><subject>Burn-in</subject><subject>burn-in reduction</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>CMOS technology</subject><subject>Computer simulation</subject><subject>Costs</subject><subject>Design engineering</subject><subject>Devices</subject><subject>Industry standards</subject><subject>integral circuit testing</subject><subject>Integrated circuit testing</subject><subject>Life estimation</subject><subject>Semiconductor device manufacture</subject><subject>Statistical analysis</subject><subject>Stress</subject><subject>Stresses</subject><subject>Temperature</subject><subject>voltage stress</subject><subject>Wafer scale integration</subject><subject>Weibull analysis</subject><issn>0740-7475</issn><issn>2168-2356</issn><issn>1558-1918</issn><issn>2168-2364</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2006</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp90U1LAzEQBuAgCtbqyaOXxYMIsjWz-dyj1E-oCFLpMWTTpE3Z7tZNVui_N6WC4MHTwPAwzMyL0DngEQAub1_vp6MCYz5i-AANgDGZQwnyEA2woDgXVLBjdBLCCmMMwPkAzd7tvDe-WWRV3zW5b7Lo1zaLy67tF8ts6RfL_Kuto17YLMTOhpBFG2Kmm3k2s77q6zr1dfQheqPr1Nf1Nvhwio6croM9-6lD9PH4MB0_55O3p5fx3SQ3hNKYU106N680KzhxhYUKwBHmBOHU8rQ-ccwZQR2vSm34HGPBiDBQaWsqLaUjQ3S1n7vp2s8-babWPhhb17qxbR9UISUFwkSC1_9C4AIIBSxxopd_6KpNz0lnqBIKKDCXZUI3e2S6NoTOOrXp_Fp3WwVY7cJQKQy1C0Ox3ciLvfbW2l_JgQgpyDcHTIWM</recordid><startdate>20060301</startdate><enddate>20060301</enddate><creator>Zakaria, M.F.</creator><creator>Kassim, Z.A.</creator><creator>Ooi, M.P.-L.</creator><creator>Demidenko, S.</creator><general>IEEE Computer Society</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>F28</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20060301</creationdate><title>Reducing burn-in time through high-voltage stress test and Weibull statistical analysis</title><author>Zakaria, M.F. ; Kassim, Z.A. ; Ooi, M.P.-L. ; Demidenko, S.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c344t-4a9ffdba5263f2e1b11f35f7364e65583f5fc74f6b9ac6d007537c1baecba88f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2006</creationdate><topic>Burn-in</topic><topic>burn-in reduction</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>CMOS technology</topic><topic>Computer simulation</topic><topic>Costs</topic><topic>Design engineering</topic><topic>Devices</topic><topic>Industry standards</topic><topic>integral circuit testing</topic><topic>Integrated circuit testing</topic><topic>Life estimation</topic><topic>Semiconductor device manufacture</topic><topic>Statistical analysis</topic><topic>Stress</topic><topic>Stresses</topic><topic>Temperature</topic><topic>voltage stress</topic><topic>Wafer scale integration</topic><topic>Weibull analysis</topic><toplevel>online_resources</toplevel><creatorcontrib>Zakaria, M.F.</creatorcontrib><creatorcontrib>Kassim, Z.A.</creatorcontrib><creatorcontrib>Ooi, M.P.-L.</creatorcontrib><creatorcontrib>Demidenko, S.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE design & test of computers</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zakaria, M.F.</au><au>Kassim, Z.A.</au><au>Ooi, M.P.-L.</au><au>Demidenko, S.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Reducing burn-in time through high-voltage stress test and Weibull statistical analysis</atitle><jtitle>IEEE design & test of computers</jtitle><stitle>MDT</stitle><date>2006-03-01</date><risdate>2006</risdate><volume>23</volume><issue>2</issue><spage>88</spage><epage>98</epage><pages>88-98</pages><issn>0740-7475</issn><issn>2168-2356</issn><eissn>1558-1918</eissn><eissn>2168-2364</eissn><coden>IDTCEC</coden><abstract>To guarantee an industry standard of reliability in ICs, manufacturers incorporate special testing techniques into the circuit manufacturing process. For most electronic devices, the specific reliability required is quite high, often producing a lifespan of several years. Testing such devices for reliability under normal operating conditions would require a very long period of time to gather the data necessary for modeling the device's failure characteristics. Under this scenario, a device might become obsolete by the time the manufacturer could guarantee its reliability. High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in.</abstract><cop>Los Alamitos</cop><pub>IEEE Computer Society</pub><doi>10.1109/MDT.2006.50</doi><tpages>11</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0740-7475 |
| ispartof | IEEE design & test of computers, 2006-03, Vol.23 (2), p.88-98 |
| issn | 0740-7475 2168-2356 1558-1918 2168-2364 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_1671341080 |
| source | IEEE Electronic Library (IEL) |
| subjects | Burn-in burn-in reduction Circuit testing Circuits CMOS technology Computer simulation Costs Design engineering Devices Industry standards integral circuit testing Integrated circuit testing Life estimation Semiconductor device manufacture Statistical analysis Stress Stresses Temperature voltage stress Wafer scale integration Weibull analysis |
| title | Reducing burn-in time through high-voltage stress test and Weibull statistical analysis |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T02%3A08%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Reducing%20burn-in%20time%20through%20high-voltage%20stress%20test%20and%20Weibull%20statistical%20analysis&rft.jtitle=IEEE%20design%20&%20test%20of%20computers&rft.au=Zakaria,%20M.F.&rft.date=2006-03-01&rft.volume=23&rft.issue=2&rft.spage=88&rft.epage=98&rft.pages=88-98&rft.issn=0740-7475&rft.eissn=1558-1918&rft.coden=IDTCEC&rft_id=info:doi/10.1109/MDT.2006.50&rft_dat=%3Cproquest_RIE%3E1671341080%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=912120689&rft_id=info:pmid/&rft_ieee_id=1613787&rfr_iscdi=true |