A Realistic Early-Stage Power Grid Verification Algorithm Based on Hierarchical Constraints

Power grid verification has become an indispensable step to guarantee a functional and robust chip design. Vectorless power grid verification methods, by solving linear programming (LP) problems under current constraints, enable worst-case voltage drop predictions at an early stage of design when th...

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Veröffentlicht in:	IEEE transactions on computer-aided design of integrated circuits and systems 2012-01, Vol.31 (1), p.109-120
Hauptverfasser:	Yuanzhe Wang, Xiang Hu, Chung-Kuan Cheng, Pang, G. K. H., Ngai Wong
Format:	Artikel
Sprache:	eng
Schlagworte:	Algorithm design and analysis Algorithms Complexity Complexity theory Computational modeling Design engineering Drains Electric potential Hierarchical constraints Integrated circuit modeling Mathematical analysis Mathematical models model order reduction Power grids Prediction algorithms Studies submodular polyhedron vectorless power grid verification Vectors Voltage drop worst-case voltage drop
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