Adaptive Circuits for the 0.5-V Nanoscale CMOS Era

The minimum operating voltage, Vmin, of nanoscale CMOS LSIs is investigated to breach the 1-V wall that we are facing in the 65-nm device generation, and open the door to the below 0.5-V era. A new method using speed variation is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the...

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Veröffentlicht in:	IEICE Transactions on Electronics 2010/03/01, Vol.E93.C(3), pp.216-233
Hauptverfasser:	ITOH, Kiyoo, YAMAOKA, Masanao, OSHIMA, Takashi
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuits CMOS Devices DRAM FD-SOI FinFET Inverters minimum operating voltage MOSFETs Nanocomposites Nanomaterials Nanostructure SRAM
Online-Zugang:	Volltext
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