Structural FSM traversal
This paper discusses a "structural" technique for traversing the state space of a finite state machine (FSM) and its application to equivalence checking of sequential circuits. The key ingredient to a state-space traversal is a data structure to represent state sets. In structural FSM, tra...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 2004-05, Vol.23 (5), p.598-619, Article 598 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 23 |
| creator | Stoffel, D. Wedler, M. Warkentin, P. Kunz, W. |
| description | This paper discusses a "structural" technique for traversing the state space of a finite state machine (FSM) and its application to equivalence checking of sequential circuits. The key ingredient to a state-space traversal is a data structure to represent state sets. In structural FSM, traversal-state sets are represented noncanonically and implicitly as gate netlists. First, we present an exact algorithm, which is based on an iterative expansion of the FSM into time frames and a network-decomposition procedure serving the same purpose as an existential quantification operation. Then, we discuss approximative algorithms for the application of structural FSM traversal to sequential equivalence checking. We theoretically analyze the properties of the exact as well as the approximative algorithms. Finally, we give details on the implementation of a sequential equivalence checker and present experimental results that demonstrate the effectiveness of the proposed approach for equivalence checking of optimized and retimed circuits. |
| doi_str_mv | 10.1109/TCAD.2004.826552 |
| format | Article |
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The key ingredient to a state-space traversal is a data structure to represent state sets. In structural FSM, traversal-state sets are represented noncanonically and implicitly as gate netlists. First, we present an exact algorithm, which is based on an iterative expansion of the FSM into time frames and a network-decomposition procedure serving the same purpose as an existential quantification operation. Then, we discuss approximative algorithms for the application of structural FSM traversal to sequential equivalence checking. We theoretically analyze the properties of the exact as well as the approximative algorithms. Finally, we give details on the implementation of a sequential equivalence checker and present experimental results that demonstrate the effectiveness of the proposed approach for equivalence checking of optimized and retimed circuits.</description><subject>Algorithm design and analysis</subject><subject>Algorithms</subject><subject>Approximation</subject><subject>Automata</subject><subject>Binary decision diagrams</subject><subject>Boolean functions</subject><subject>Checkers</subject><subject>Circuits</subject><subject>Computer aided design</subject><subject>Data structures</subject><subject>Design engineering</subject><subject>Finite state machines</subject><subject>Formal verification</subject><subject>Gates</subject><subject>Iterative algorithms</subject><subject>Reachability analysis</subject><subject>Sequential circuits</subject><subject>State-space methods</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kD1LA0EQQBdRMEb7gE2wEJuLM_txO1uGaFSIWCTWy7q3gQuXXNy9E_z3XjhBSGE1zXszzGNshDBBBHO_mk0fJhxATojnSvETNkAjdCZR4SkbANeUAWg4ZxcpbQBQKm4GbLRsYuubNrpqPF--jpvovkJMrrpkZ2tXpXD1O4fsff64mj1ni7enl9l0kXmheJNJWeRGay2EwvAhCghcCwoKKeRAWq9BUhHIG0cSjC84acRcFb7QgXtRiCG77ffuY_3ZhtTYbZl8qCq3C3WbLKdcoATowLt_Qcw1cmNImA69OUI3dRt33RuWSJAhBdRB0EM-1inFsLb7WG5d_LYI9pDUHpLaQ1LbJ-2U_EjxZeOast512crqP_G6F8sQwt8dblBpJX4A6AN_pg</recordid><startdate>20040501</startdate><enddate>20040501</enddate><creator>Stoffel, D.</creator><creator>Wedler, M.</creator><creator>Warkentin, P.</creator><creator>Kunz, W.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>F28</scope><scope>FR3</scope><scope>7TB</scope></search><sort><creationdate>20040501</creationdate><title>Structural FSM traversal</title><author>Stoffel, D. ; Wedler, M. ; Warkentin, P. ; Kunz, W.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c352t-44d697773351eb3d0e2738e518e60877f048de8c9a8409cd2871165dcd7e2c3d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Algorithm design and analysis</topic><topic>Algorithms</topic><topic>Approximation</topic><topic>Automata</topic><topic>Binary decision diagrams</topic><topic>Boolean functions</topic><topic>Checkers</topic><topic>Circuits</topic><topic>Computer aided design</topic><topic>Data structures</topic><topic>Design engineering</topic><topic>Finite state machines</topic><topic>Formal verification</topic><topic>Gates</topic><topic>Iterative algorithms</topic><topic>Reachability analysis</topic><topic>Sequential circuits</topic><topic>State-space methods</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Stoffel, D.</creatorcontrib><creatorcontrib>Wedler, M.</creatorcontrib><creatorcontrib>Warkentin, P.</creatorcontrib><creatorcontrib>Kunz, W.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Stoffel, D.</au><au>Wedler, M.</au><au>Warkentin, P.</au><au>Kunz, W.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Structural FSM traversal</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>2004-05-01</date><risdate>2004</risdate><volume>23</volume><issue>5</issue><spage>598</spage><epage>619</epage><pages>598-619</pages><artnum>598</artnum><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>This paper discusses a "structural" technique for traversing the state space of a finite state machine (FSM) and its application to equivalence checking of sequential circuits. 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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 2004-05, Vol.23 (5), p.598-619, Article 598 |
| issn | 0278-0070 1937-4151 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithm design and analysis Algorithms Approximation Automata Binary decision diagrams Boolean functions Checkers Circuits Computer aided design Data structures Design engineering Finite state machines Formal verification Gates Iterative algorithms Reachability analysis Sequential circuits State-space methods |
| title | Structural FSM traversal |
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