On the physical mechanism of the NROM memory erase
The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide b...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on electron devices 2004-10, Vol.51 (10), p.1593-1599 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1599 |
|---|---|
| container_issue | 10 |
| container_start_page | 1593 |
| container_title | IEEE transactions on electron devices |
| container_volume | 51 |
| creator | Larcher, L. Pavan, P. Eitan, B. |
| description | The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide barrier) by means of standard two-dimensional simulations and ad-hoc models reproducing hole and electron transport mechanisms across the oxide not included in standard device simulators. Hot-hole injection will be identified as the actual conduction mechanism of NROM erase, and two compact models capable to describe the main characteristics of NROM erase current will be developed. |
| doi_str_mv | 10.1109/TED.2004.834897 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_1671297193</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1337169</ieee_id><sourcerecordid>1671297193</sourcerecordid><originalsourceid>FETCH-LOGICAL-c446t-13e2ada795a5f34cd7f99eb16a60dc55ed9059a4acf7f71d2fd7b5dcfd2917723</originalsourceid><addsrcrecordid>eNp9kE1LAzEQhoMoWKtnD14WQfGybSafm6PU-gHVgtRzSLMJ3dLdrUl76L83dQsFD56GmfeZgXkQugY8AMBqOBs_DQjGbFBQVih5gnrAucyVYOIU9TCGIle0oOfoIsZlagVjpIfItMk2C5etF7tYWbPKamcXpqlinbX-N_n4nL6nad2GXeaCie4SnXmziu7qUPvo63k8G73mk-nL2-hxklvGxCYH6ogpjVTccE-ZLaVXys1BGIFLy7krFebKMGO99BJK4ks556X1JVEgJaF9dN_dXYf2e-viRtdVtG61Mo1rt1GTgnFS8D348C8IQgJREhRN6O0fdNluQ5Pe0EXBkkbKZYKGHWRDG2NwXq9DVZuw04D13rVOrvXete5cp427w1kTk0QfTGOreFwTIAEYT9xNx1XOuWNMqQSh6A9AVoUc</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>884109357</pqid></control><display><type>article</type><title>On the physical mechanism of the NROM memory erase</title><source>IEEE Electronic Library (IEL)</source><creator>Larcher, L. ; Pavan, P. ; Eitan, B.</creator><creatorcontrib>Larcher, L. ; Pavan, P. ; Eitan, B.</creatorcontrib><description>The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide barrier) by means of standard two-dimensional simulations and ad-hoc models reproducing hole and electron transport mechanisms across the oxide not included in standard device simulators. Hot-hole injection will be identified as the actual conduction mechanism of NROM erase, and two compact models capable to describe the main characteristics of NROM erase current will be developed.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2004.834897</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Charge carrier lifetime ; Computer simulation ; Design. Technologies. Operation analysis. Testing ; Devices ; Electron emission ; Electronics ; Emission analysis ; Exact sciences and technology ; Hot carriers ; Integrated circuit modeling ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Oxides ; Read only memories ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Semiconductor memories ; Simulators ; Testing, measurement, noise and reliability ; Tunneling ; Two dimensional</subject><ispartof>IEEE transactions on electron devices, 2004-10, Vol.51 (10), p.1593-1599</ispartof><rights>2004 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c446t-13e2ada795a5f34cd7f99eb16a60dc55ed9059a4acf7f71d2fd7b5dcfd2917723</citedby><cites>FETCH-LOGICAL-c446t-13e2ada795a5f34cd7f99eb16a60dc55ed9059a4acf7f71d2fd7b5dcfd2917723</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1337169$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1337169$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=16171145$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Larcher, L.</creatorcontrib><creatorcontrib>Pavan, P.</creatorcontrib><creatorcontrib>Eitan, B.</creatorcontrib><title>On the physical mechanism of the NROM memory erase</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide barrier) by means of standard two-dimensional simulations and ad-hoc models reproducing hole and electron transport mechanisms across the oxide not included in standard device simulators. Hot-hole injection will be identified as the actual conduction mechanism of NROM erase, and two compact models capable to describe the main characteristics of NROM erase current will be developed.</description><subject>Applied sciences</subject><subject>Charge carrier lifetime</subject><subject>Computer simulation</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>Electron emission</subject><subject>Electronics</subject><subject>Emission analysis</subject><subject>Exact sciences and technology</subject><subject>Hot carriers</subject><subject>Integrated circuit modeling</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Oxides</subject><subject>Read only memories</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Semiconductor memories</subject><subject>Simulators</subject><subject>Testing, measurement, noise and reliability</subject><subject>Tunneling</subject><subject>Two dimensional</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kE1LAzEQhoMoWKtnD14WQfGybSafm6PU-gHVgtRzSLMJ3dLdrUl76L83dQsFD56GmfeZgXkQugY8AMBqOBs_DQjGbFBQVih5gnrAucyVYOIU9TCGIle0oOfoIsZlagVjpIfItMk2C5etF7tYWbPKamcXpqlinbX-N_n4nL6nad2GXeaCie4SnXmziu7qUPvo63k8G73mk-nL2-hxklvGxCYH6ogpjVTccE-ZLaVXys1BGIFLy7krFebKMGO99BJK4ks556X1JVEgJaF9dN_dXYf2e-viRtdVtG61Mo1rt1GTgnFS8D348C8IQgJREhRN6O0fdNluQ5Pe0EXBkkbKZYKGHWRDG2NwXq9DVZuw04D13rVOrvXete5cp427w1kTk0QfTGOreFwTIAEYT9xNx1XOuWNMqQSh6A9AVoUc</recordid><startdate>20041001</startdate><enddate>20041001</enddate><creator>Larcher, L.</creator><creator>Pavan, P.</creator><creator>Eitan, B.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20041001</creationdate><title>On the physical mechanism of the NROM memory erase</title><author>Larcher, L. ; Pavan, P. ; Eitan, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c446t-13e2ada795a5f34cd7f99eb16a60dc55ed9059a4acf7f71d2fd7b5dcfd2917723</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Charge carrier lifetime</topic><topic>Computer simulation</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>Electron emission</topic><topic>Electronics</topic><topic>Emission analysis</topic><topic>Exact sciences and technology</topic><topic>Hot carriers</topic><topic>Integrated circuit modeling</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Oxides</topic><topic>Read only memories</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Semiconductor memories</topic><topic>Simulators</topic><topic>Testing, measurement, noise and reliability</topic><topic>Tunneling</topic><topic>Two dimensional</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Larcher, L.</creatorcontrib><creatorcontrib>Pavan, P.</creatorcontrib><creatorcontrib>Eitan, B.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Larcher, L.</au><au>Pavan, P.</au><au>Eitan, B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>On the physical mechanism of the NROM memory erase</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2004-10-01</date><risdate>2004</risdate><volume>51</volume><issue>10</issue><spage>1593</spage><epage>1599</epage><pages>1593-1599</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>The purpose of this paper is to investigate the physical mechanism of NROM memory erase. Three conduction mechanisms potentially responsible of NROM erase will be analyzed (tunneling and emission of electrons through both bottom and top oxide, tunneling and injection of holes over the bottom oxide barrier) by means of standard two-dimensional simulations and ad-hoc models reproducing hole and electron transport mechanisms across the oxide not included in standard device simulators. Hot-hole injection will be identified as the actual conduction mechanism of NROM erase, and two compact models capable to describe the main characteristics of NROM erase current will be developed.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2004.834897</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 2004-10, Vol.51 (10), p.1593-1599 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_1671297193 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Charge carrier lifetime Computer simulation Design. Technologies. Operation analysis. Testing Devices Electron emission Electronics Emission analysis Exact sciences and technology Hot carriers Integrated circuit modeling Integrated circuits Integrated circuits by function (including memories and processors) Oxides Read only memories Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductor memories Simulators Testing, measurement, noise and reliability Tunneling Two dimensional |
| title | On the physical mechanism of the NROM memory erase |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T01%3A04%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=On%20the%20physical%20mechanism%20of%20the%20NROM%20memory%20erase&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Larcher,%20L.&rft.date=2004-10-01&rft.volume=51&rft.issue=10&rft.spage=1593&rft.epage=1599&rft.pages=1593-1599&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2004.834897&rft_dat=%3Cproquest_RIE%3E1671297193%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=884109357&rft_id=info:pmid/&rft_ieee_id=1337169&rfr_iscdi=true |