A numerical procedure for simulating delamination growth on interfaces of interconnect structures
A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with tran...
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Veröffentlicht in: | Microelectronics and reliability 2012-07, Vol.52 (7), p.1464-1474 |
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creator | Chiu, Tz-Cheng Chen, Chun-Hui |
description | A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure. |
doi_str_mv | 10.1016/j.microrel.2012.03.006 |
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In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.</description><identifier>ISSN: 0026-2714</identifier><identifier>EISSN: 1872-941X</identifier><identifier>DOI: 10.1016/j.microrel.2012.03.006</identifier><identifier>CODEN: MCRLAS</identifier><language>eng</language><publisher>Kidlington: Elsevier Ltd</publisher><subject>Applied sciences ; Computer simulation ; Crack propagation ; Delaminating ; Design. Technologies. Operation analysis. Testing ; Electronics ; Evolution ; Exact sciences and technology ; Fatigue failure ; Fracture mechanics ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Mathematical models ; Microelectronic fabrication (materials and surfaces technology) ; Semiconductor electronics. Microelectronics. Optoelectronics. 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In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.</description><subject>Applied sciences</subject><subject>Computer simulation</subject><subject>Crack propagation</subject><subject>Delaminating</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Evolution</subject><subject>Exact sciences and technology</subject><subject>Fatigue failure</subject><subject>Fracture mechanics</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Mathematical models</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><issn>0026-2714</issn><issn>1872-941X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><recordid>eNqFkM1r3DAQxUVJoJuPf6HoUujFzozkla1bQ2g-YKGXFnITsjxOtdhSKtkt-e-jsNtce5p58GYe78fYJ4QaAdXVvp69SzHRVAtAUYOsAdQHtsGuFZVu8PGEbQCEqkSLzUd2lvMeAFpA3DB7zcM6U_LOTvw5RUfDmoiPMfHs53Wyiw9PfKDJzj4UEQN_SvHv8ouXzYeF0mgdZR7Hg3IxBHILz0ta3VJe5Qt2Otop0-VxnrOft99-3NxXu-93DzfXu8rJdrtUshGSrO5Vq0gqZxH7rUWQfQetw04PCgehrZZ6BE29VaIHKTuwTbPtRD_Ic_bl8Le0-L1SXszss6NpsoHimg2qFoXGLWCxqoO1YMs50Wiek59tejEI5o2p2Zt_TM0bUwPSFKbl8PMxw-YCbEw2OJ_fr4UChE5D8X09-KgU_uMpmew8hQLXp0LHDNH_L-oV5DyR9Q</recordid><startdate>20120701</startdate><enddate>20120701</enddate><creator>Chiu, Tz-Cheng</creator><creator>Chen, Chun-Hui</creator><general>Elsevier Ltd</general><general>Elsevier</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20120701</creationdate><title>A numerical procedure for simulating delamination growth on interfaces of interconnect structures</title><author>Chiu, Tz-Cheng ; Chen, Chun-Hui</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c375t-3423ea9b676e36ca11b5a103b807c189d61d29a939f09eba62b03380a44582bd3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Applied sciences</topic><topic>Computer simulation</topic><topic>Crack propagation</topic><topic>Delaminating</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Evolution</topic><topic>Exact sciences and technology</topic><topic>Fatigue failure</topic><topic>Fracture mechanics</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Mathematical models</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chiu, Tz-Cheng</creatorcontrib><creatorcontrib>Chen, Chun-Hui</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Microelectronics and reliability</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chiu, Tz-Cheng</au><au>Chen, Chun-Hui</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A numerical procedure for simulating delamination growth on interfaces of interconnect structures</atitle><jtitle>Microelectronics and reliability</jtitle><date>2012-07-01</date><risdate>2012</risdate><volume>52</volume><issue>7</issue><spage>1464</spage><epage>1474</epage><pages>1464-1474</pages><issn>0026-2714</issn><eissn>1872-941X</eissn><coden>MCRLAS</coden><abstract>A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.</abstract><cop>Kidlington</cop><pub>Elsevier Ltd</pub><doi>10.1016/j.microrel.2012.03.006</doi><tpages>11</tpages></addata></record> |
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subjects | Applied sciences Computer simulation Crack propagation Delaminating Design. Technologies. Operation analysis. Testing Electronics Evolution Exact sciences and technology Fatigue failure Fracture mechanics Integrated circuits Integrated circuits by function (including memories and processors) Mathematical models Microelectronic fabrication (materials and surfaces technology) Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
title | A numerical procedure for simulating delamination growth on interfaces of interconnect structures |
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