A numerical procedure for simulating delamination growth on interfaces of interconnect structures

A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with tran...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Microelectronics and reliability 2012-07, Vol.52 (7), p.1464-1474
Hauptverfasser: Chiu, Tz-Cheng, Chen, Chun-Hui
Format: Artikel
Sprache:eng
Schlagworte:
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 1474
container_issue 7
container_start_page 1464
container_title Microelectronics and reliability
container_volume 52
creator Chiu, Tz-Cheng
Chen, Chun-Hui
description A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.
doi_str_mv 10.1016/j.microrel.2012.03.006
format Article
fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1671291501</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><els_id>S0026271412000807</els_id><sourcerecordid>1671291501</sourcerecordid><originalsourceid>FETCH-LOGICAL-c375t-3423ea9b676e36ca11b5a103b807c189d61d29a939f09eba62b03380a44582bd3</originalsourceid><addsrcrecordid>eNqFkM1r3DAQxUVJoJuPf6HoUujFzozkla1bQ2g-YKGXFnITsjxOtdhSKtkt-e-jsNtce5p58GYe78fYJ4QaAdXVvp69SzHRVAtAUYOsAdQHtsGuFZVu8PGEbQCEqkSLzUd2lvMeAFpA3DB7zcM6U_LOTvw5RUfDmoiPMfHs53Wyiw9PfKDJzj4UEQN_SvHv8ouXzYeF0mgdZR7Hg3IxBHILz0ta3VJe5Qt2Otop0-VxnrOft99-3NxXu-93DzfXu8rJdrtUshGSrO5Vq0gqZxH7rUWQfQetw04PCgehrZZ6BE29VaIHKTuwTbPtRD_Ic_bl8Le0-L1SXszss6NpsoHimg2qFoXGLWCxqoO1YMs50Wiek59tejEI5o2p2Zt_TM0bUwPSFKbl8PMxw-YCbEw2OJ_fr4UChE5D8X09-KgU_uMpmew8hQLXp0LHDNH_L-oV5DyR9Q</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>1671291501</pqid></control><display><type>article</type><title>A numerical procedure for simulating delamination growth on interfaces of interconnect structures</title><source>Elsevier ScienceDirect Journals Complete</source><creator>Chiu, Tz-Cheng ; Chen, Chun-Hui</creator><creatorcontrib>Chiu, Tz-Cheng ; Chen, Chun-Hui</creatorcontrib><description>A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.</description><identifier>ISSN: 0026-2714</identifier><identifier>EISSN: 1872-941X</identifier><identifier>DOI: 10.1016/j.microrel.2012.03.006</identifier><identifier>CODEN: MCRLAS</identifier><language>eng</language><publisher>Kidlington: Elsevier Ltd</publisher><subject>Applied sciences ; Computer simulation ; Crack propagation ; Delaminating ; Design. Technologies. Operation analysis. Testing ; Electronics ; Evolution ; Exact sciences and technology ; Fatigue failure ; Fracture mechanics ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Mathematical models ; Microelectronic fabrication (materials and surfaces technology) ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><ispartof>Microelectronics and reliability, 2012-07, Vol.52 (7), p.1464-1474</ispartof><rights>2012 Elsevier Ltd</rights><rights>2015 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c375t-3423ea9b676e36ca11b5a103b807c189d61d29a939f09eba62b03380a44582bd3</citedby><cites>FETCH-LOGICAL-c375t-3423ea9b676e36ca11b5a103b807c189d61d29a939f09eba62b03380a44582bd3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://www.sciencedirect.com/science/article/pii/S0026271412000807$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,776,780,3537,27901,27902,65306</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=26010890$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Chiu, Tz-Cheng</creatorcontrib><creatorcontrib>Chen, Chun-Hui</creatorcontrib><title>A numerical procedure for simulating delamination growth on interfaces of interconnect structures</title><title>Microelectronics and reliability</title><description>A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.</description><subject>Applied sciences</subject><subject>Computer simulation</subject><subject>Crack propagation</subject><subject>Delaminating</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Evolution</subject><subject>Exact sciences and technology</subject><subject>Fatigue failure</subject><subject>Fracture mechanics</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Mathematical models</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><issn>0026-2714</issn><issn>1872-941X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2012</creationdate><recordtype>article</recordtype><recordid>eNqFkM1r3DAQxUVJoJuPf6HoUujFzozkla1bQ2g-YKGXFnITsjxOtdhSKtkt-e-jsNtce5p58GYe78fYJ4QaAdXVvp69SzHRVAtAUYOsAdQHtsGuFZVu8PGEbQCEqkSLzUd2lvMeAFpA3DB7zcM6U_LOTvw5RUfDmoiPMfHs53Wyiw9PfKDJzj4UEQN_SvHv8ouXzYeF0mgdZR7Hg3IxBHILz0ta3VJe5Qt2Otop0-VxnrOft99-3NxXu-93DzfXu8rJdrtUshGSrO5Vq0gqZxH7rUWQfQetw04PCgehrZZ6BE29VaIHKTuwTbPtRD_Ic_bl8Le0-L1SXszss6NpsoHimg2qFoXGLWCxqoO1YMs50Wiek59tejEI5o2p2Zt_TM0bUwPSFKbl8PMxw-YCbEw2OJ_fr4UChE5D8X09-KgU_uMpmew8hQLXp0LHDNH_L-oV5DyR9Q</recordid><startdate>20120701</startdate><enddate>20120701</enddate><creator>Chiu, Tz-Cheng</creator><creator>Chen, Chun-Hui</creator><general>Elsevier Ltd</general><general>Elsevier</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>20120701</creationdate><title>A numerical procedure for simulating delamination growth on interfaces of interconnect structures</title><author>Chiu, Tz-Cheng ; Chen, Chun-Hui</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c375t-3423ea9b676e36ca11b5a103b807c189d61d29a939f09eba62b03380a44582bd3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2012</creationdate><topic>Applied sciences</topic><topic>Computer simulation</topic><topic>Crack propagation</topic><topic>Delaminating</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Evolution</topic><topic>Exact sciences and technology</topic><topic>Fatigue failure</topic><topic>Fracture mechanics</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Mathematical models</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Chiu, Tz-Cheng</creatorcontrib><creatorcontrib>Chen, Chun-Hui</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Microelectronics and reliability</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Chiu, Tz-Cheng</au><au>Chen, Chun-Hui</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A numerical procedure for simulating delamination growth on interfaces of interconnect structures</atitle><jtitle>Microelectronics and reliability</jtitle><date>2012-07-01</date><risdate>2012</risdate><volume>52</volume><issue>7</issue><spage>1464</spage><epage>1474</epage><pages>1464-1474</pages><issn>0026-2714</issn><eissn>1872-941X</eissn><coden>MCRLAS</coden><abstract>A fracture mechanics based numerical approach is developed for modeling delamination growth on materials interfaces in integrated circuit (IC) interconnects. In this approach, the heterogeneous interconnect structures neighboring the cracked interface are approximated by homogenized layers with transversely isotropic elastic properties. Evolution of the interface crack under fatigue condition is modeled by using an incremental approach, in which the fracture mechanics parameters including the strain energy release rate, the normalized stress intensity factors and phase angles are first estimated by post-processing finite element solutions. The fracture mechanics parameters along the curvilinear front of the interface crack are then substituted into a steady-state fatigue crack growth model for obtaining the crack growth increments. The process is repeated to simulate subsequent crack growth for predicting interconnect structural reliability under fatigue condition. The evolution of an interface corner crack in a back-end-of-line (BEOL) Cu/low-k interconnect structure under temperature cycling condition is considered as an application example of the procedure.</abstract><cop>Kidlington</cop><pub>Elsevier Ltd</pub><doi>10.1016/j.microrel.2012.03.006</doi><tpages>11</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0026-2714
ispartof Microelectronics and reliability, 2012-07, Vol.52 (7), p.1464-1474
issn 0026-2714
1872-941X
language eng
recordid cdi_proquest_miscellaneous_1671291501
source Elsevier ScienceDirect Journals Complete
subjects Applied sciences
Computer simulation
Crack propagation
Delaminating
Design. Technologies. Operation analysis. Testing
Electronics
Evolution
Exact sciences and technology
Fatigue failure
Fracture mechanics
Integrated circuits
Integrated circuits by function (including memories and processors)
Mathematical models
Microelectronic fabrication (materials and surfaces technology)
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
title A numerical procedure for simulating delamination growth on interfaces of interconnect structures
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T16%3A41%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20numerical%20procedure%20for%20simulating%20delamination%20growth%20on%20interfaces%20of%20interconnect%20structures&rft.jtitle=Microelectronics%20and%20reliability&rft.au=Chiu,%20Tz-Cheng&rft.date=2012-07-01&rft.volume=52&rft.issue=7&rft.spage=1464&rft.epage=1474&rft.pages=1464-1474&rft.issn=0026-2714&rft.eissn=1872-941X&rft.coden=MCRLAS&rft_id=info:doi/10.1016/j.microrel.2012.03.006&rft_dat=%3Cproquest_cross%3E1671291501%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=1671291501&rft_id=info:pmid/&rft_els_id=S0026271412000807&rfr_iscdi=true