A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS

A third-order continuous-time multibit (4 bit) Delta capital sigma ADC for wireless applications is implemented in a 0.13- mu m CMOS process. It is shown that the power consumption can be considerably reduced by using a tracking ADC composed of three comparators with interpolation instead of using a...

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