An efficient and simple compact modeling approach for 3-D interconnects with IC's stack global electrical context consideration

3D integration is considered to be the most promising solution to overcome challenges encountered currently in planar technologies. As an emerging technology, electrical compact models are notably required for 3D interconnects, including Through-Silicon Via (TSV), to accurately evaluate 3D system performances. However, 3D integration implies that the whole electrical context must be considered such as current paths or couplings between chip elements. Simple closed-form expressions describing the electrical models of some 3D ICs propagation lines are reported in this paper. The efficient modeling methodology described in this work is applied to various 3D test structures. The modeling approach's effectiveness is validated in a wide frequency range, from DC to 10 GHz. Nevertheless, in the high frequency-domain, the substrate coupling effects are no longer negligible and must be also included in the overall 3D system electrical description. As a consequence, a substrate extraction method, relying on the Transmission Line Method (TLM) and the Green functions, is also proposed to model substrate networks. This extraction method is validated in the case of a coplanar waveguide atop a high-resistive substrate. Finally, the method is applied for timing analyses by means of Eye Diagrams performed on different TSV matrix configurations.