Series Expansion based Efficient Architectures for Double Precision Floating Point Division

Floating point division is a complex operation among all floating point arithmetic; it is also an area and a performance dominating unit. This paper presents double precision floating point division architectures on FPGA platforms. The designs are area optimized, running at higher clock speed, with...

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Veröffentlicht in:	Circuits, systems, and signal processing systems, and signal processing, 2014-11, Vol.33 (11), p.3499-3526
Hauptverfasser:	Jaiswal, Manish Kumar, Cheung, Ray C. C., Balakrishnan, M., Paul, Kolin
Format:	Artikel
Sprache:	eng
Schlagworte:	Architecture Circuits and Systems Computer engineering Design engineering Division Electrical Engineering Electronics and Microelectronics Engineering Field programmable gate arrays Floating point arithmetic Hardware Instrumentation Mathematical functions Multipliers Signal,Image and Speech Processing Tables (data)
Online-Zugang:	Volltext
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