Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems
A holistic power saving concept for ultra-low-power microcontroller (MCU) systems involving application requirements, system architecture, and circuit design techniques is presented. The key of this concept is a digitally enhanced low dropout regulator (LDO) supplying the MCU digital core. By making...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2014-11, Vol.22 (11), p.2287-2296 |
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| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 22 |
| creator | Lueders, Michael Eversmann, Bjoern Gerber, Johannes Huber, Korbinian Kuhn, Ruediger Zwerg, Michael Schmitt-Landsiedel, Doris Brederlow, Ralf |
| description | A holistic power saving concept for ultra-low-power microcontroller (MCU) systems involving application requirements, system architecture, and circuit design techniques is presented. The key of this concept is a digitally enhanced low dropout regulator (LDO) supplying the MCU digital core. By making use of known system power information, the LDO digitally adapts its maximum current drive capability up to 2.56 mA while its quiescent current is as low as 650 nA in light load conditions. In this way, the power management overhead is drastically reduced when operating at low clock speeds enabling system energy savings of 31% at 1 MHz. At the same time, a drastic reduction of the LDO output capacitance enables ultra-low-power consumption during sleep and energy efficient wake-up, resulting in system energy savings up to a factor of 4.6. |
| doi_str_mv | 10.1109/TVLSI.2013.2290083 |
| format | Article |
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The key of this concept is a digitally enhanced low dropout regulator (LDO) supplying the MCU digital core. By making use of known system power information, the LDO digitally adapts its maximum current drive capability up to 2.56 mA while its quiescent current is as low as 650 nA in light load conditions. In this way, the power management overhead is drastically reduced when operating at low clock speeds enabling system energy savings of 31% at 1 MHz. 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(IEEE) Nov 2014</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c398t-e9e9ba86b3e280c6e5a89dd28116fde60ad22a302a9e2ab1eedb24bf7f9d94283</citedby><cites>FETCH-LOGICAL-c398t-e9e9ba86b3e280c6e5a89dd28116fde60ad22a302a9e2ab1eedb24bf7f9d94283</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6680706$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6680706$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Lueders, Michael</creatorcontrib><creatorcontrib>Eversmann, Bjoern</creatorcontrib><creatorcontrib>Gerber, Johannes</creatorcontrib><creatorcontrib>Huber, Korbinian</creatorcontrib><creatorcontrib>Kuhn, Ruediger</creatorcontrib><creatorcontrib>Zwerg, Michael</creatorcontrib><creatorcontrib>Schmitt-Landsiedel, Doris</creatorcontrib><creatorcontrib>Brederlow, Ralf</creatorcontrib><title>Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>A holistic power saving concept for ultra-low-power microcontroller (MCU) systems involving application requirements, system architecture, and circuit design techniques is presented. The key of this concept is a digitally enhanced low dropout regulator (LDO) supplying the MCU digital core. By making use of known system power information, the LDO digitally adapts its maximum current drive capability up to 2.56 mA while its quiescent current is as low as 650 nA in light load conditions. In this way, the power management overhead is drastically reduced when operating at low clock speeds enabling system energy savings of 31% at 1 MHz. At the same time, a drastic reduction of the LDO output capacitance enables ultra-low-power consumption during sleep and energy efficient wake-up, resulting in system energy savings up to a factor of 4.6.</description><subject>Capacitance</subject><subject>Circuit design</subject><subject>Clocks</subject><subject>Digitally enhanced analog</subject><subject>Energy conservation</subject><subject>Energy consumption</subject><subject>energy harvesting</subject><subject>Energy management</subject><subject>fully integrated voltage regulator</subject><subject>Power demand</subject><subject>Power management</subject><subject>power management unit</subject><subject>Random access memory</subject><subject>Sleep</subject><subject>Switches</subject><subject>Temperature measurement</subject><subject>ultra-low-power microcontroller</subject><subject>Very large scale integration</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdkE1Lw0AQhhdRsFb_gF4WvHhJ3Y9ks3ss8asQUWjrddkkk3ZLPupuQum_N7XFg3OZgXneYXgQuqVkQilRj4uvdD6bMEL5hDFFiORnaESjKA7UUOfDTAQPJKPkEl15vyGEhqEiI6SnLl_bDvKud6bCpilwYl3e2w4_gberBi8gXzf2uwePy9bhz3YHDr-bxqyghqbDbYmXVedMkLa74LRNlni-9x3U_hpdlKbycHPqY7R8eV4kb0H68TpLpmmQcyW7ABSozEiRcWCS5AIiI1VRMEmpKAsQxBSMGU6YUcBMRgGKjIVZGZeqUCGTfIwejne3rj382una-hyqyjTQ9l5TETLGaBzxAb3_h27a3jXDdwNFhZKcczJQ7EjlrvXeQam3ztbG7TUl-uBc_zrXB-f65HwI3R1DFgD-AkJIEg_-fwAxYX3R</recordid><startdate>20141101</startdate><enddate>20141101</enddate><creator>Lueders, Michael</creator><creator>Eversmann, Bjoern</creator><creator>Gerber, Johannes</creator><creator>Huber, Korbinian</creator><creator>Kuhn, Ruediger</creator><creator>Zwerg, Michael</creator><creator>Schmitt-Landsiedel, Doris</creator><creator>Brederlow, Ralf</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The key of this concept is a digitally enhanced low dropout regulator (LDO) supplying the MCU digital core. By making use of known system power information, the LDO digitally adapts its maximum current drive capability up to 2.56 mA while its quiescent current is as low as 650 nA in light load conditions. In this way, the power management overhead is drastically reduced when operating at low clock speeds enabling system energy savings of 31% at 1 MHz. At the same time, a drastic reduction of the LDO output capacitance enables ultra-low-power consumption during sleep and energy efficient wake-up, resulting in system energy savings up to a factor of 4.6.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2013.2290083</doi><tpages>10</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Capacitance Circuit design Clocks Digitally enhanced analog Energy conservation Energy consumption energy harvesting Energy management fully integrated voltage regulator Power demand Power management power management unit Random access memory Sleep Switches Temperature measurement ultra-low-power microcontroller Very large scale integration |
| title | Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems |
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