Crossbar RRAM Arrays: Selector Device Requirements During Write Operation
A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage...
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Veröffentlicht in: | IEEE transactions on electron devices 2014-08, Vol.61 (8), p.2820-2826 |
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description | A comprehensive analysis of write operations (SET and RESET) in a resistance-change memory (resistive random access memory) crossbar array is carried out. Three types of resistive switching memory cells-nonlinear, rectifying-SET, and rectifying-RESET-are compared with each other in terms of voltage delivery, current delivery, and power consumption. Two different write schemes, V/2 and V/3, were considered, and the V/2 write scheme is preferred due to much lower power consumption. A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation. |
doi_str_mv | 10.1109/TED.2014.2327514 |
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A simple numerical method was developed that simulates entire current flows and node voltages within a crossbar array and provides a quantitative tool for the accurate analysis of crossbar arrays and guidelines for developing reliable write operation.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2014.2327514</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Arrays ; Crossbar ; Devices ; Electric potential ; Guidelines ; Junctions ; Leakage currents ; Power consumption ; Power demand ; Random access memory ; Reliability ; Resistance ; resistive random access memory (RRAM) ; selector device ; Selectors ; sneak path ; Switches ; Voltage ; write margin ; write scheme</subject><ispartof>IEEE transactions on electron devices, 2014-08, Vol.61 (8), p.2820-2826</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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subjects | Arrays Crossbar Devices Electric potential Guidelines Junctions Leakage currents Power consumption Power demand Random access memory Reliability Resistance resistive random access memory (RRAM) selector device Selectors sneak path Switches Voltage write margin write scheme |
title | Crossbar RRAM Arrays: Selector Device Requirements During Write Operation |
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