A High Speed Explicit Pulsed Dual Edge Triggered D Flip Flop

This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is comp...

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Veröffentlicht in:	International journal of computer applications 2014-01, Vol.93 (17)
Hauptverfasser:	Joshi, Manan, Chauhan, D S, Kaushik, B K
Format:	Artikel
Sprache:	eng
Schlagworte:	Clocks Computer simulation Delay Dynamics Flip-flops High speed Mathematical models Pulse generators
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container_title	International journal of computer applications
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creator	Joshi, Manan Chauhan, D S Kaushik, B K
description	This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation results overall improvements of 12. 67% and 10. 15% are observed in delay and power delay product respectively.
doi_str_mv	10.5120/16425-5607
format	Article
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subjects	Clocks Computer simulation Delay Dynamics Flip-flops High speed Mathematical models Pulse generators
title	A High Speed Explicit Pulsed Dual Edge Triggered D Flip Flop
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