Realizing logic gates with time-delayed synthetic genetic networks
We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this de...
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Veröffentlicht in: | Nonlinear dynamics 2014-04, Vol.76 (1), p.431-439 |
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creator | Sharma, Amit Kohar, Vivek Shrimali, Manish Dev Sinha, Sudeshna |
description | We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this delay can either enhance or diminish logic behavior, depending on its functional form. Lastly, we show that the desired response to inputs can be induced, even in the absence of noise, by time delay alone. |
doi_str_mv | 10.1007/s11071-013-1136-9 |
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fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_1551045431</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>2259476233</sourcerecordid><originalsourceid>FETCH-LOGICAL-c349t-be5b439bea3e744684854ee8e805be8bb12eac12078c259945fb1cc0d3fc2b4f3</originalsourceid><addsrcrecordid>eNp1kEtLw0AUhQdRsFZ_gLuAGzej984jySy1-IKCIArdDcn0Jk1Nk5pJKfXXOzWCILi5Z_Odw-Vj7BzhCgGSa48ICXJAyRFlzM0BG6FOJBexmR2yERihOBiYHbMT75cAIAWkI3b7QlldfVZNGdVtWbmozHry0bbqF1FfrYjPqc52NI_8rukX1O8Jar4z3G3bvftTdlRktaeznxyzt_u718kjnz4_PE1uptxJZXqek86VNDllkhKl4lSlWhGllILOKc1zFJQ5FJCkTmhjlC5ydA7msnAiV4Ucs8thd921HxvyvV1V3lFdZw21G29RawSllcSAXvxBl-2ma8J3VoRtlcRCykDhQLmu9b6jwq67apV1O4tg91btYNUGq3Zv1ZrQEUPHB7Ypqftd_r_0Bb7JegQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>2259476233</pqid></control><display><type>article</type><title>Realizing logic gates with time-delayed synthetic genetic networks</title><source>SpringerLink Journals - AutoHoldings</source><creator>Sharma, Amit ; Kohar, Vivek ; Shrimali, Manish Dev ; Sinha, Sudeshna</creator><creatorcontrib>Sharma, Amit ; Kohar, Vivek ; Shrimali, Manish Dev ; Sinha, Sudeshna</creatorcontrib><description>We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this delay can either enhance or diminish logic behavior, depending on its functional form. Lastly, we show that the desired response to inputs can be induced, even in the absence of noise, by time delay alone.</description><identifier>ISSN: 0924-090X</identifier><identifier>EISSN: 1573-269X</identifier><identifier>DOI: 10.1007/s11071-013-1136-9</identifier><language>eng</language><publisher>Dordrecht: Springer Netherlands</publisher><subject>Automotive Engineering ; Classical Mechanics ; Control ; Delay ; Dynamical Systems ; Engineering ; Gates ; Genes ; Genetics ; Logic ; Logic circuits ; Mechanical Engineering ; Networks ; Noise ; Original Paper ; Time delay ; Time lag ; Vibration</subject><ispartof>Nonlinear dynamics, 2014-04, Vol.76 (1), p.431-439</ispartof><rights>Springer Science+Business Media Dordrecht 2013</rights><rights>Nonlinear Dynamics is a copyright of Springer, (2013). All Rights Reserved.</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c349t-be5b439bea3e744684854ee8e805be8bb12eac12078c259945fb1cc0d3fc2b4f3</citedby><cites>FETCH-LOGICAL-c349t-be5b439bea3e744684854ee8e805be8bb12eac12078c259945fb1cc0d3fc2b4f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktopdf>$$Uhttps://link.springer.com/content/pdf/10.1007/s11071-013-1136-9$$EPDF$$P50$$Gspringer$$H</linktopdf><linktohtml>$$Uhttps://link.springer.com/10.1007/s11071-013-1136-9$$EHTML$$P50$$Gspringer$$H</linktohtml><link.rule.ids>314,780,784,27924,27925,41488,42557,51319</link.rule.ids></links><search><creatorcontrib>Sharma, Amit</creatorcontrib><creatorcontrib>Kohar, Vivek</creatorcontrib><creatorcontrib>Shrimali, Manish Dev</creatorcontrib><creatorcontrib>Sinha, Sudeshna</creatorcontrib><title>Realizing logic gates with time-delayed synthetic genetic networks</title><title>Nonlinear dynamics</title><addtitle>Nonlinear Dyn</addtitle><description>We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this delay can either enhance or diminish logic behavior, depending on its functional form. Lastly, we show that the desired response to inputs can be induced, even in the absence of noise, by time delay alone.</description><subject>Automotive Engineering</subject><subject>Classical Mechanics</subject><subject>Control</subject><subject>Delay</subject><subject>Dynamical Systems</subject><subject>Engineering</subject><subject>Gates</subject><subject>Genes</subject><subject>Genetics</subject><subject>Logic</subject><subject>Logic circuits</subject><subject>Mechanical Engineering</subject><subject>Networks</subject><subject>Noise</subject><subject>Original Paper</subject><subject>Time delay</subject><subject>Time lag</subject><subject>Vibration</subject><issn>0924-090X</issn><issn>1573-269X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>AFKRA</sourceid><sourceid>BENPR</sourceid><sourceid>CCPQU</sourceid><sourceid>DWQXO</sourceid><recordid>eNp1kEtLw0AUhQdRsFZ_gLuAGzej984jySy1-IKCIArdDcn0Jk1Nk5pJKfXXOzWCILi5Z_Odw-Vj7BzhCgGSa48ICXJAyRFlzM0BG6FOJBexmR2yERihOBiYHbMT75cAIAWkI3b7QlldfVZNGdVtWbmozHry0bbqF1FfrYjPqc52NI_8rukX1O8Jar4z3G3bvftTdlRktaeznxyzt_u718kjnz4_PE1uptxJZXqek86VNDllkhKl4lSlWhGllILOKc1zFJQ5FJCkTmhjlC5ydA7msnAiV4Ucs8thd921HxvyvV1V3lFdZw21G29RawSllcSAXvxBl-2ma8J3VoRtlcRCykDhQLmu9b6jwq67apV1O4tg91btYNUGq3Zv1ZrQEUPHB7Ypqftd_r_0Bb7JegQ</recordid><startdate>20140401</startdate><enddate>20140401</enddate><creator>Sharma, Amit</creator><creator>Kohar, Vivek</creator><creator>Shrimali, Manish Dev</creator><creator>Sinha, Sudeshna</creator><general>Springer Netherlands</general><general>Springer Nature B.V</general><scope>AAYXX</scope><scope>CITATION</scope><scope>8FE</scope><scope>8FG</scope><scope>ABJCF</scope><scope>AFKRA</scope><scope>BENPR</scope><scope>BGLVJ</scope><scope>CCPQU</scope><scope>DWQXO</scope><scope>HCIFZ</scope><scope>L6V</scope><scope>M7S</scope><scope>PQEST</scope><scope>PQQKQ</scope><scope>PQUKI</scope><scope>PRINS</scope><scope>PTHSS</scope><scope>7SC</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>KR7</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20140401</creationdate><title>Realizing logic gates with time-delayed synthetic genetic networks</title><author>Sharma, Amit ; Kohar, Vivek ; Shrimali, Manish Dev ; Sinha, Sudeshna</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c349t-be5b439bea3e744684854ee8e805be8bb12eac12078c259945fb1cc0d3fc2b4f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>Automotive Engineering</topic><topic>Classical Mechanics</topic><topic>Control</topic><topic>Delay</topic><topic>Dynamical Systems</topic><topic>Engineering</topic><topic>Gates</topic><topic>Genes</topic><topic>Genetics</topic><topic>Logic</topic><topic>Logic circuits</topic><topic>Mechanical Engineering</topic><topic>Networks</topic><topic>Noise</topic><topic>Original Paper</topic><topic>Time delay</topic><topic>Time lag</topic><topic>Vibration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Sharma, Amit</creatorcontrib><creatorcontrib>Kohar, Vivek</creatorcontrib><creatorcontrib>Shrimali, Manish Dev</creatorcontrib><creatorcontrib>Sinha, Sudeshna</creatorcontrib><collection>CrossRef</collection><collection>ProQuest SciTech Collection</collection><collection>ProQuest Technology Collection</collection><collection>Materials Science & Engineering Collection</collection><collection>ProQuest Central UK/Ireland</collection><collection>ProQuest Central</collection><collection>Technology Collection</collection><collection>ProQuest One Community College</collection><collection>ProQuest Central Korea</collection><collection>SciTech Premium Collection</collection><collection>ProQuest Engineering Collection</collection><collection>Engineering Database</collection><collection>ProQuest One Academic Eastern Edition (DO NOT USE)</collection><collection>ProQuest One Academic</collection><collection>ProQuest One Academic UKI Edition</collection><collection>ProQuest Central China</collection><collection>Engineering Collection</collection><collection>Computer and Information Systems Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Civil Engineering Abstracts</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Nonlinear dynamics</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Sharma, Amit</au><au>Kohar, Vivek</au><au>Shrimali, Manish Dev</au><au>Sinha, Sudeshna</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Realizing logic gates with time-delayed synthetic genetic networks</atitle><jtitle>Nonlinear dynamics</jtitle><stitle>Nonlinear Dyn</stitle><date>2014-04-01</date><risdate>2014</risdate><volume>76</volume><issue>1</issue><spage>431</spage><epage>439</epage><pages>431-439</pages><issn>0924-090X</issn><eissn>1573-269X</eissn><abstract>We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this delay can either enhance or diminish logic behavior, depending on its functional form. Lastly, we show that the desired response to inputs can be induced, even in the absence of noise, by time delay alone.</abstract><cop>Dordrecht</cop><pub>Springer Netherlands</pub><doi>10.1007/s11071-013-1136-9</doi><tpages>9</tpages></addata></record> |
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subjects | Automotive Engineering Classical Mechanics Control Delay Dynamical Systems Engineering Gates Genes Genetics Logic Logic circuits Mechanical Engineering Networks Noise Original Paper Time delay Time lag Vibration |
title | Realizing logic gates with time-delayed synthetic genetic networks |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T07%3A32%3A13IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Realizing%20logic%20gates%20with%20time-delayed%20synthetic%20genetic%20networks&rft.jtitle=Nonlinear%20dynamics&rft.au=Sharma,%20Amit&rft.date=2014-04-01&rft.volume=76&rft.issue=1&rft.spage=431&rft.epage=439&rft.pages=431-439&rft.issn=0924-090X&rft.eissn=1573-269X&rft_id=info:doi/10.1007/s11071-013-1136-9&rft_dat=%3Cproquest_cross%3E2259476233%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=2259476233&rft_id=info:pmid/&rfr_iscdi=true |