Realizing logic gates with time-delayed synthetic genetic networks

We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this de...

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Veröffentlicht in:Nonlinear dynamics 2014-04, Vol.76 (1), p.431-439
Hauptverfasser: Sharma, Amit, Kohar, Vivek, Shrimali, Manish Dev, Sinha, Sudeshna
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container_title Nonlinear dynamics
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creator Sharma, Amit
Kohar, Vivek
Shrimali, Manish Dev
Sinha, Sudeshna
description We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this delay can either enhance or diminish logic behavior, depending on its functional form. Lastly, we show that the desired response to inputs can be induced, even in the absence of noise, by time delay alone.
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subjects Automotive Engineering
Classical Mechanics
Control
Delay
Dynamical Systems
Engineering
Gates
Genes
Genetics
Logic
Logic circuits
Mechanical Engineering
Networks
Noise
Original Paper
Time delay
Time lag
Vibration
title Realizing logic gates with time-delayed synthetic genetic networks
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