Realizing logic gates with time-delayed synthetic genetic networks

We demonstrate the realization of fundamental logic operations, as well as a memory element, with engineered delayed synthetic gene networks. Further, we investigate the effect of time delay in different kinds of processes, on the operational range of this biological logic gate. We show that this delay can either enhance or diminish logic behavior, depending on its functional form. Lastly, we show that the desired response to inputs can be induced, even in the absence of noise, by time delay alone.