Towards third generation pixel readout chips

We present concepts and prototyping results towards a third generation pixel readout chip. We consider the 130nm feature size FE-I4 chip, in production for the ATLAS IBL upgrade, to be a second generation chip. A third generation chip would have to go significantly further. A possible direction is to make the IC design generic so that different experiments can configure it to meet significantly different requirements, without the need for everybody to develop their own ASIC from the ground up. In terms of target technology, a demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in 65nm CMOS and irradiated with protons in December 2011 and May 2012.