A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique

In this Letter, 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when...

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Veröffentlicht in:	Analog integrated circuits and signal processing 2014-04, Vol.79 (1), p.183-189
Hauptverfasser:	Song, Junyoung, Hwang, Sewook, Kim, Tae-Chan, Kim, Chulwoo
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuits and Systems Clocks CMOS Consumption Digital Electrical Engineering Engineering Jitter Mixed Signal Letter Phase error Reduction Signal processing Signal,Image and Speech Processing
Online-Zugang:	Volltext
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