28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique
We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro usin...
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| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2014-03, Vol.22 (3), p.575-584 |
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| creator | Umemoto, Yukiko Nii, Koji Ishikawa, Jiro Yabuuchi, Makoto Okamoto, Kazuyoshi Tsukamoto, Yasumasa Tanaka, Shinji Tanaka, Koji Matsumura, Tetsuya Mori, Kazutaka Yanagisawa, Kazumasa |
| description | We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros. |
| doi_str_mv | 10.1109/TVLSI.2013.2246201 |
| format | Article |
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It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2013.2246201</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>28 nm ; 2T read only memory (ROM) bitcell ; Access time ; Bias ; CMOS ; Dynamics ; embedded ROM ; High speed ; low-power source bias control ; Masks ; memory ; Read only ; Very large scale integration ; Voltage</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2014-03, Vol.22 (3), p.575-584</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Mar 2014</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c377t-8b361d5e8e003b288119dc4af9a5ea0006ddfb12f7a63a7f7a6a6193eef390373</citedby><cites>FETCH-LOGICAL-c377t-8b361d5e8e003b288119dc4af9a5ea0006ddfb12f7a63a7f7a6a6193eef390373</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/6491497$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/6491497$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Umemoto, Yukiko</creatorcontrib><creatorcontrib>Nii, Koji</creatorcontrib><creatorcontrib>Ishikawa, Jiro</creatorcontrib><creatorcontrib>Yabuuchi, Makoto</creatorcontrib><creatorcontrib>Okamoto, Kazuyoshi</creatorcontrib><creatorcontrib>Tsukamoto, Yasumasa</creatorcontrib><creatorcontrib>Tanaka, Shinji</creatorcontrib><creatorcontrib>Tanaka, Koji</creatorcontrib><creatorcontrib>Matsumura, Tetsuya</creatorcontrib><creatorcontrib>Mori, Kazutaka</creatorcontrib><creatorcontrib>Yanagisawa, Kazumasa</creatorcontrib><title>28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.</description><subject>28 nm</subject><subject>2T read only memory (ROM) bitcell</subject><subject>Access time</subject><subject>Bias</subject><subject>CMOS</subject><subject>Dynamics</subject><subject>embedded ROM</subject><subject>High speed</subject><subject>low-power source bias control</subject><subject>Masks</subject><subject>memory</subject><subject>Read only</subject><subject>Very large scale integration</subject><subject>Voltage</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2014</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNpdUU1v1DAQjRBIlJY_AJeREBKXbMd2YsfHsnxV2qpVm8Ix8joT6pI4rZ0I7e_hj-J0qx7qy5vD-5jxy7J3DFeMoT6uf26uTlccmVhxXsg0vMgOWFmqXKf3Ms0oRV5xhq-zNzHeIrKi0HiQ_eMV-AFK_AgX418K-SW1s3X-N6xHPxk7UQtnJv6BSzItnPt-B2c0jCGBsWGEX266AVwpnvu455xYSzFC7QaC67g48RoujAvw2U2W-h6Mb-HLzpvB2ZTSz4OHq3EOlhLDxIfgMPZQk73x7n6mo-xVZ_pIbx_xMLv-9rVe_8g3599P1yeb3AqlprzaCsnakipCFFteVYzp1ham06Ykg4iybbst450yUhi1gJFMC6JOaBRKHGaf9r53YUyxcWoGF5eNjadxjg0rOWqZJCxRPzyj3qYLfNousVByKRVfDPmelX4qxkBdcxfcYMKuYdgsvTUPvTVLb81jb0n0fi9yRPQkkIVmhVbiP8IPkgg</recordid><startdate>20140301</startdate><enddate>20140301</enddate><creator>Umemoto, Yukiko</creator><creator>Nii, Koji</creator><creator>Ishikawa, Jiro</creator><creator>Yabuuchi, Makoto</creator><creator>Okamoto, Kazuyoshi</creator><creator>Tsukamoto, Yasumasa</creator><creator>Tanaka, Shinji</creator><creator>Tanaka, Koji</creator><creator>Matsumura, Tetsuya</creator><creator>Mori, Kazutaka</creator><creator>Yanagisawa, Kazumasa</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20140301</creationdate><title>28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique</title><author>Umemoto, Yukiko ; Nii, Koji ; Ishikawa, Jiro ; Yabuuchi, Makoto ; Okamoto, Kazuyoshi ; Tsukamoto, Yasumasa ; Tanaka, Shinji ; Tanaka, Koji ; Matsumura, Tetsuya ; Mori, Kazutaka ; Yanagisawa, Kazumasa</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c377t-8b361d5e8e003b288119dc4af9a5ea0006ddfb12f7a63a7f7a6a6193eef390373</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2014</creationdate><topic>28 nm</topic><topic>2T read only memory (ROM) bitcell</topic><topic>Access time</topic><topic>Bias</topic><topic>CMOS</topic><topic>Dynamics</topic><topic>embedded ROM</topic><topic>High speed</topic><topic>low-power source bias control</topic><topic>Masks</topic><topic>memory</topic><topic>Read only</topic><topic>Very large scale integration</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Umemoto, Yukiko</creatorcontrib><creatorcontrib>Nii, Koji</creatorcontrib><creatorcontrib>Ishikawa, Jiro</creatorcontrib><creatorcontrib>Yabuuchi, Makoto</creatorcontrib><creatorcontrib>Okamoto, Kazuyoshi</creatorcontrib><creatorcontrib>Tsukamoto, Yasumasa</creatorcontrib><creatorcontrib>Tanaka, Shinji</creatorcontrib><creatorcontrib>Tanaka, Koji</creatorcontrib><creatorcontrib>Matsumura, Tetsuya</creatorcontrib><creatorcontrib>Mori, Kazutaka</creatorcontrib><creatorcontrib>Yanagisawa, Kazumasa</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Umemoto, Yukiko</au><au>Nii, Koji</au><au>Ishikawa, Jiro</au><au>Yabuuchi, Makoto</au><au>Okamoto, Kazuyoshi</au><au>Tsukamoto, Yasumasa</au><au>Tanaka, Shinji</au><au>Tanaka, Koji</au><au>Matsumura, Tetsuya</au><au>Mori, Kazutaka</au><au>Yanagisawa, Kazumasa</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2014-03-01</date><risdate>2014</risdate><volume>22</volume><issue>3</issue><spage>575</spage><epage>584</epage><pages>575-584</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>We propose a new 2T mask read only memory (ROM) with dynamic column source bias control technique, which enables achieving both high-speed operation and low power consumption. It is also possible to overcome the inherent problem of crosstalk between the bitlines. The fabricated 128-kb ROM macro using 28-nm high- k and metal-gate CMOS bulk technology realizes 0.72 ns read access time at the typical 0.85-V supply voltage, which is comparable to that of recent high-speed embedded static random access memories. The measured dynamic power dissipation is reduced by 50% compared to the conventional 2T ROM. The standby leakage can also be reduced to half that of conventional macros.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2013.2246201</doi><tpages>10</tpages></addata></record> |
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| subjects | 28 nm 2T read only memory (ROM) bitcell Access time Bias CMOS Dynamics embedded ROM High speed low-power source bias control Masks memory Read only Very large scale integration Voltage |
| title | 28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique |
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